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Format verilog code with verible-verilog-format #280

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Oct 22, 2024
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Format verilog code with verible-verilog-format #280

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e04aacd
Add make target to format verilog code using verible-verilog-format
jthornblad Oct 22, 2024
3514d7e
FPGA: Format verilog code
jthornblad Oct 22, 2024
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40 changes: 36 additions & 4 deletions hw/application_fpga/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -87,7 +87,6 @@ VERILOG_SRCS = \
$(P)/core/ram/rtl/ram.v \
$(P)/core/rom/rtl/rom.v \
$(P)/core/fw_ram/rtl/fw_ram.v \
$(P)/core/picorv32/rtl/picorv32.v \
$(P)/core/timer/rtl/timer_core.v \
$(P)/core/timer/rtl/timer.v \
$(P)/core/uds/rtl/uds.v \
Expand All @@ -101,6 +100,10 @@ VERILOG_SRCS = \
$(P)/core/uart/rtl/uart.v \
$(P)/core/trng/rtl/rosc.v

# PicoRV32 verilog source file
PICORV32_SRCS = \
$(P)/core/picorv32/rtl/picorv32.v

FIRMWARE_DEPS = \
$(P)/fw/tk1_mem.h \
$(P)/fw/tk1/types.h \
Expand Down Expand Up @@ -239,7 +242,7 @@ LINT_FLAGS = \
--timescale 1ns/1ns \
-DNO_ICE40_DEFAULT_ASSIGNMENTS

lint: $(FPGA_SRC) $(VERILOG_SRCS) $(ICE40_SIM_CELLS)
lint: $(FPGA_SRC) $(VERILOG_SRCS) $(PICORV32_SRCS) $(ICE40_SIM_CELLS)
$(LINT) $(LINT_FLAGS) \
-DBRAM_FW_SIZE=$(BRAM_FW_SIZE) \
-DFIRMWARE_HEX=\"$(P)/firmware.hex\" \
Expand All @@ -252,10 +255,38 @@ lint: $(FPGA_SRC) $(VERILOG_SRCS) $(ICE40_SIM_CELLS)
|| { cat lint_issues.txt; exit 1; }
.PHONY: lint

#-------------------------------------------------------------------
# Source formatting.
#-------------------------------------------------------------------
FORMAT = verible-verilog-format

FORMAT_FLAGS = \
--indentation_spaces=2 \
--wrap_end_else_clauses=true \
--inplace

CHECK_FORMAT_FLAGS = \
--indentation_spaces=2 \
--wrap_end_else_clauses=true \
--inplace \
--verify

fmt: $(FPGA_SRC) $(VERILATOR_FPGA_SRC) $(VERILOG_SRCS)
$(FORMAT) $(FORMAT_FLAGS) $^
.PHONY: fmt

# Temporary fix using grep, since the verible with --verify flag only returns
# error if the last file is malformatted.
checkfmt: $(FPGA_SRC) $(VERILATOR_FPGA_SRC) $(VERILOG_SRCS)
$(FORMAT) $(CHECK_FORMAT_FLAGS) $^ 2>&1 | \
grep "Needs formatting" && exit 1 || true
.PHONY: checkfmt

#-------------------------------------------------------------------
# Build Verilator compiled simulation for the design.
#-------------------------------------------------------------------
verilator: $(VERILATOR_FPGA_SRC) $(VERILOG_SRCS) firmware.hex $(ICE40_SIM_CELLS) \
verilator: $(VERILATOR_FPGA_SRC) $(VERILOG_SRCS) $(PICORV32_SRCS) \
firmware.hex $(ICE40_SIM_CELLS) \
$(P)/tb/application_fpga_verilator.cc
verilator \
--timescale 1ns/1ns \
Expand Down Expand Up @@ -296,7 +327,8 @@ tb:

YOSYS_FLAG ?=

synth.json: $(FPGA_SRC) $(VERILOG_SRCS) bram_fw.hex $(P)/data/uds.hex $(P)/data/udi.hex
synth.json: $(FPGA_SRC) $(VERILOG_SRCS) $(PICORV32_SRCS) bram_fw.hex \
$(P)/data/uds.hex $(P)/data/udi.hex
$(YOSYS_PATH)yosys \
-v3 \
-l synth.txt \
Expand Down
109 changes: 56 additions & 53 deletions hw/application_fpga/core/clk_reset_gen/rtl/clk_reset_gen.v
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Original file line number Diff line number Diff line change
Expand Up @@ -16,33 +16,34 @@

`default_nettype none

module clk_reset_gen #(parameter RESET_CYCLES = 200)
(
input wire sys_reset,
module clk_reset_gen #(
parameter RESET_CYCLES = 200
) (
input wire sys_reset,

output wire clk,
output wire rst_n
);
output wire clk,
output wire rst_n
);


//----------------------------------------------------------------
// Registers with associated wires.
//----------------------------------------------------------------
reg [7 : 0] rst_ctr_reg = 8'h0;
reg [7 : 0] rst_ctr_new;
reg rst_ctr_we;
reg [7 : 0] rst_ctr_reg = 8'h0;
reg [7 : 0] rst_ctr_new;
reg rst_ctr_we;

reg rst_n_reg = 1'h0;
reg rst_n_new;
reg rst_n_reg = 1'h0;
reg rst_n_new;

reg sys_reset_reg;
reg sys_reset_reg;


//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
wire hfosc_clk;
wire pll_clk;
wire hfosc_clk;
wire pll_clk;


//----------------------------------------------------------------
Expand All @@ -58,8 +59,13 @@ module clk_reset_gen #(parameter RESET_CYCLES = 200)

// Use the FPGA internal High Frequency OSCillator as clock source.
// 00: 48MHz, 01: 24MHz, 10: 12MHz, 11: 6MHz
SB_HFOSC #(.CLKHF_DIV("0b10")
) hfosc_inst (.CLKHFPU(1'b1),.CLKHFEN(1'b1),.CLKHF(hfosc_clk));
SB_HFOSC #(
.CLKHF_DIV("0b10")
) hfosc_inst (
.CLKHFPU(1'b1),
.CLKHFEN(1'b1),
.CLKHF (hfosc_clk)
);


// Use a PLL to generate a new clock frequency based on the HFOSC clock.
Expand All @@ -74,63 +80,60 @@ module clk_reset_gen #(parameter RESET_CYCLES = 200)
//
// (12000000 * (55 + 1)) / (2^5 * (0 + 1)) = 21000000
SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"),
.DIVR(4'd0), // DIVR = 0
.DIVF(7'd55), // DIVF = 55
.DIVQ(3'd5), // DIVQ = 5
.FILTER_RANGE(3'b001) // FILTER_RANGE = 1
) pll_inst (
.RESETB(1'b1),
.BYPASS(1'b0),
.REFERENCECLK(hfosc_clk),
.PLLOUTCORE(pll_clk)
);
.FEEDBACK_PATH("SIMPLE"),
.DIVR(4'd0), // DIVR = 0
.DIVF(7'd55), // DIVF = 55
.DIVQ(3'd5), // DIVQ = 5
.FILTER_RANGE(3'b001) // FILTER_RANGE = 1
) pll_inst (
.RESETB(1'b1),
.BYPASS(1'b0),
.REFERENCECLK(hfosc_clk),
.PLLOUTCORE(pll_clk)
);


// Use a Global Buffer to distribute the clock.
SB_GB gb_inst (
.USER_SIGNAL_TO_GLOBAL_BUFFER (pll_clk),
.GLOBAL_BUFFER_OUTPUT (clk)
);
.USER_SIGNAL_TO_GLOBAL_BUFFER(pll_clk),
.GLOBAL_BUFFER_OUTPUT(clk)
);

/* verilator lint_on PINMISSING */


//----------------------------------------------------------------
// reg_update.
//----------------------------------------------------------------
always @(posedge clk)
begin : reg_update
rst_n_reg <= rst_n_new;
sys_reset_reg <= sys_reset;
always @(posedge clk) begin : reg_update
rst_n_reg <= rst_n_new;
sys_reset_reg <= sys_reset;

if (rst_ctr_we)
rst_ctr_reg <= rst_ctr_new;
end
if (rst_ctr_we) rst_ctr_reg <= rst_ctr_new;
end


//----------------------------------------------------------------
// rst_logic.
//----------------------------------------------------------------
always @*
begin : rst_logic
rst_n_new = 1'h1;
always @* begin : rst_logic
rst_n_new = 1'h1;
rst_ctr_new = 8'h0;
rst_ctr_we = 1'h0;

if (sys_reset_reg) begin
rst_ctr_new = 8'h0;
rst_ctr_we = 1'h0;

if (sys_reset_reg) begin
rst_ctr_new = 8'h0;
rst_ctr_we = 1'h1;
end

else if (rst_ctr_reg < RESET_CYCLES) begin
rst_n_new = 1'h0;
rst_ctr_new = rst_ctr_reg + 1'h1;
rst_ctr_we = 1'h1;
end
rst_ctr_we = 1'h1;
end

else if (rst_ctr_reg < RESET_CYCLES) begin
rst_n_new = 1'h0;
rst_ctr_new = rst_ctr_reg + 1'h1;
rst_ctr_we = 1'h1;
end
end

endmodule // reset_gen
endmodule // reset_gen

//======================================================================
// EOF reset_gen.v
Expand Down
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