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Format verilog code with verible-verilog-format #280

Merged
merged 2 commits into from
Oct 22, 2024
Merged

Format verilog code with verible-verilog-format #280

merged 2 commits into from
Oct 22, 2024
+3,617 −3,687

Commits on Oct 22, 2024

  1. Add make target to format verilog code using verible-verilog-format 

    Flags:
        --indentation_spaces=2
        --wrap_end_else_clauses=true

Verify flag, used in checkfmt, only returns error if the last file is
not formatted, temporary fix implemented with grep.
    @jthornblad @dehanj
    jthornblad authored and dehanj committed Oct 22, 2024
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  2. FPGA: Format verilog code

    @jthornblad @dehanj
    jthornblad authored and dehanj committed Oct 22, 2024
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