v0.2.13

0.2.13 - 2023-09-19

Fixed

• tc_sram_xilinx: Fix be assignment

v0.2.12

0.2.12 - 2023-08-12

Changed

• tc_sram_xilinx: Support ByteWidth != 8

v0.2.11

0.2.11 - 2022-12-12

Added

• tc_clk_or2: A new generic tech cell for balanced clock OR-gates.
• tc_clk_mux2: Added warning about misusing tc_clk_mux2 cells.

v0.2.10

0.2.10 - 2022-11-20

Added

• tc_sram_impl: Wrapper for tc_sram with implementation-specific keys and IO

Changed

• tc_sram: Improve simulation performance

Fixed

• tc_clk_xilinx: Add IS_FUNCTIONAL parameter to match tc_clk_gating interface

v0.2.9

0.2.9 - 2022-03-17

Changed

• Added optional IS_FUNCTIONAL flag to tc_clk_gating cell to optionally mark them as not required for functionality.

v0.2.6

0.2.6 - 2021-10-04

Added

• pad_functional_xilinx

Fixed

• Bender targets

Removed

• Deprecated xilinx clk_cells replaced by wrappers

v0.2.4

0.2.4 - 2021-02-04

Fixed

• Add deprecated/pulp_clk_cells_xilinx.sv to Bender.yml

v0.2.3

0.2.3 - 2021-01-28

Fixed

• tc_sram_xilinx: Remove unsupported string type from SimInit parameter.
• IPApproX: Add tc_sram to src_files.yml for proper compilation with IPApproX

v0.2.2

Fixed

• Bender: Add deprecated pulp_clock_gating_async for compatibility to udma_core.

v0.2.1

Added

-Bender: Add rtl/tc_sram to target rtl, to prevent overwriting of target specific implementations.

Fixed

• tc_sram: Drop string literal from parameter SimInit definition as synopsys throws an elaboration error.
• tc_clk:tc_clk_delay: Add Verilator and synthesis guards.