-
Notifications
You must be signed in to change notification settings - Fork 24
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
FPGA: Add system reset API #242
Conversation
secworks
commented
Jun 24, 2024
Note that this implementation does not look at the mode. This means that both a device app and FW could trigger reset. Not sure if that is something want. It made the implementation less complex. Also, this function dropped the clock frequency somewhat. We could try an add a register to cut combinational logic. |
Are we missing a define in Should it be defined like this in |
Ah! Yes. And Yes. |
Did a quick test and from what I can see it works as how I expected it to. |
I'd like to see an update to |
Added description of system reset API in README. Including what is reset and what happens after a reset has been triggered. |
Add API address to trigger system reset. When written to will send system_reset signal to the reset generator, which then perform a complete reset cycle of the FPGA system. Signed-off-by: Joachim Strömbergson <[email protected]>
Rebased, squashed, verified. |