(fpga) Add transport cycle for the system reset signal

Add a register that samples the system reset signal sent from the tk1 core to the clk_pll core. This adds one cycle in transport latency. Signed-off-by: Joachim Strömbergson <[email protected]>
tillitis · Aug 20, 2024 · 74b194e · 74b194e
1 parent 7636889
commit 74b194e
Showing 1 changed file with 9 additions and 2 deletions.
diff --git a/hw/application_fpga/rtl/clk_reset_gen.v b/hw/application_fpga/rtl/clk_reset_gen.v
@@ -35,6 +35,12 @@ module clk_reset_gen #(parameter RESET_CYCLES = 200)
   reg         rst_n_reg = 1'h0;
   reg         rst_n_new;
 
+  reg         sys_reset_reg;
+
+
+  //----------------------------------------------------------------
+  // Wires.
+  //----------------------------------------------------------------
   wire        hfosc_clk;
   wire        pll_clk;
 
@@ -95,7 +101,8 @@ module clk_reset_gen #(parameter RESET_CYCLES = 200)
   //----------------------------------------------------------------
     always @(posedge clk)
       begin : reg_update
-        rst_n_reg <= rst_n_new;
+        rst_n_reg     <= rst_n_new;
+	sys_reset_reg <= sys_reset;
 
         if (rst_ctr_we)
           rst_ctr_reg <= rst_ctr_new;
@@ -111,7 +118,7 @@ module clk_reset_gen #(parameter RESET_CYCLES = 200)
       rst_ctr_new = 8'h0;
       rst_ctr_we  = 1'h0;
 
-      if (sys_reset) begin
+      if (sys_reset_reg) begin
 	rst_ctr_new = 8'h0;
 	rst_ctr_we  = 1'h1;
       end