Changing names for ram address and data randomization (retry) #229
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Do we use this or the other branch for going forward? |
Both PRs have the same digests, so that is good. This one have updates to the fw and We might want to squash a bit, i think it is enough with 2 commits. One for the FPGA, and one for FW. |
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Checked a final time. No warnings or errors. Name changes match through code, README. |
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Update: - README - testbench - Symbolic names and variables in fw - registers - port name and wires - Update fpga and fw digests Signed-off-by: Joachim Strömbergson <[email protected]>
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dehanj
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Jul 10, 2024
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This PR fixes issue #219 - again.
This PR does change the digests, but it is expected according to Yosys.