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FPGA: Add system reset API #467

FPGA: Add system reset API

FPGA: Add system reset API #467

Triggered via pull request August 20, 2024 08:42
@dehanjdehanj
synchronize #242
system_reset
Status Failure
Total duration 3m 54s
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ci.yaml

on: pull_request
build-bitstream
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build-bitstream
check-firmware
59s
check-firmware
check-verilog
1m 2s
check-verilog
build-other-firmwares
1m 3s
build-other-firmwares
check-hashes
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Process completed with exit code 2.