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Allow to build Synlig as Python module #5936

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Allow to build Synlig as Python module

Allow to build Synlig as Python module #5936

Run time

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Job Run time
Build Synlig Release
5m 1s
Build Synlig Release
5m 1s
Build Plugin
4m 42s
Build Plugin
4m 42s
Build Synlig (ASAN)
8m 42s
Build Synlig (ASAN)
8m 42s
Build Package
4m 41s
Build Package
4m 41s
Build PySynlig
9m 57s
Build PySynlig
9m 57s
Build tools
11m 47s
Build tools
11m 47s
Emit Workflow Info
0s
Emit Workflow Info
0s
Style check
1m 40s
Style check
1m 39s
Verify README Correctness (Installation From Sources)
41m 52s
Verify README Correctness (Installation From Sources)
41m 52s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)
34m 1s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)
34m 1s
Large Designs Tests / Black Parrot (ASIC synthesis)
40m 36s
Large Designs Tests / Black Parrot (ASIC synthesis)
40m 36s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)
17m 29s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)
17m 29s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
6m 32s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
6m 32s
Large Designs Tests / Ibex (Vivado synthesis)
6m 32s
Large Designs Tests / Ibex (Vivado synthesis)
6m 32s
Large Designs Tests / Ibex (F4PGA synthesis)
11m 24s
Large Designs Tests / Ibex (F4PGA synthesis)
11m 24s
Large Designs Tests / Opentitan 9d82960888 (synthesis)
25m 9s
Large Designs Tests / Opentitan 9d82960888 (synthesis)
25m 9s
Large Designs Tests / Opentitan parsing (full/top-down)
13m 38s
Large Designs Tests / Opentitan parsing (full/top-down)
13m 38s
Large Designs Tests / Opentitan parsing (quick)
5m 46s
Large Designs Tests / Opentitan parsing (quick)
5m 46s
Large Designs Tests / VeeR-EH1 (synthesis)
5m 14s
Large Designs Tests / VeeR-EH1 (synthesis)
5m 14s
Large Designs Tests / Opentitan (synthesis)
52m 28s
Large Designs Tests / Opentitan (synthesis)
52m 28s
Parsing Tests / Test read_systemverilog release
4m 22s
Parsing Tests / Test read_systemverilog release
4m 22s
Parsing Tests / Test read_uhdm release
4m 21s
Parsing Tests / Test read_uhdm release
4m 21s
Parsing Tests / Test read_systemverilog plugin
4m 26s
Parsing Tests / Test read_systemverilog plugin
4m 26s
Parsing Tests / Test read_uhdm plugin
4m 14s
Parsing Tests / Test read_uhdm plugin
4m 14s
Parsing Tests / Test read_systemverilog asan
34m 39s
Parsing Tests / Test read_systemverilog asan
34m 39s
Parsing Tests / Test read_uhdm asan
25m 19s
Parsing Tests / Test read_uhdm asan
25m 19s
Formal Verification Tests / simple
17m 44s
Formal Verification Tests / simple
17m 44s
Formal Verification Tests / sv2v
15m 27s
Formal Verification Tests / sv2v
15m 27s
Formal Verification Tests / yosys
11m 47s
Formal Verification Tests / yosys
11m 47s
Parsing Tests / Generate AST diff
1m 35s
Parsing Tests / Generate AST diff
1m 35s
Parsing Tests / Summary Generation
1m 29s
Parsing Tests / Summary Generation
1m 29s
Release Package
0s
Release Package
0s
Verify README Correctness (Download And Run Release)
0s
Verify README Correctness (Download And Run Release)
0s
14h 25m 7s