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chipsalliance / synlig Public

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Allow to build Synlig as Python module #5936

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Allow to build Synlig as Python module

Allow to build Synlig as Python module #5936

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- Usage
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Usage Workflow file

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1 warning

No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.

Large Designs Tests / VeeR-EH1 (synthesis)

succeeded Sep 27, 2024 in 5m 14s

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