Allow to build Synlig as Python module #5930

Job	Run time
Style check	1m 46s
Build Synlig Release	20m 29s
Build Plugin	19m 50s
Build Synlig (ASAN)	19m 55s
Build Package	20m 56s
Build PySynlig	24m 44s
Build tools	11m 4s
Emit Workflow Info	0s
Verify README Correctness (Installation From Sources)	42m 9s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)	16m 43s
Formal Verification Tests / simple	15m 25s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs	6m 46s
Formal Verification Tests / sv2v	17m 59s
Large Designs Tests / Black Parrot (ASIC synthesis)	38m 18s
Formal Verification Tests / yosys	14m 40s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)	21m 57s
Large Designs Tests / Ibex (Vivado synthesis)	6m 56s
Large Designs Tests / Ibex (F4PGA synthesis)	11m 25s
Large Designs Tests / Opentitan 9d82960888 (synthesis)	38m 10s
Large Designs Tests / Opentitan parsing (full/top-down)	13m 31s
Large Designs Tests / Opentitan (synthesis)	1h 0m 21s
Large Designs Tests / VeeR-EH1 (synthesis)	6m 1s
Large Designs Tests / Opentitan parsing (quick)	6m 24s
Parsing Tests / Test read_systemverilog release	4m 42s
Parsing Tests / Test read_uhdm release	4m 32s
Parsing Tests / Test read_systemverilog plugin	4m 51s
Parsing Tests / Test read_uhdm plugin	4m 39s
Parsing Tests / Test read_systemverilog asan	35m 26s
Parsing Tests / Test read_uhdm asan	25m 24s
Parsing Tests / Summary Generation	1m 27s
Parsing Tests / Generate AST diff	2m 4s
Release Package	0s
Verify README Correctness (Download And Run Release)	0s
	8h 38m 34s

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