Allow to build Synlig as Python module #5930
Triggered via pull request
September 25, 2024 11:52
kamilrakoczy
Status
Failure
Total duration
1h 25m 28s
Artifacts
45
main.yml
on: pull_request
Matrix: build-binaries
Build tools
11m 4s
Emit Workflow Info
0s
Style check
1m 46s
Verify README Correctness (Installation From Sources)
42m 9s
Matrix: Large Designs Tests / opentitan_parse_report
Matrix: Parsing Tests / parsing-tests
Large Designs Tests
/
Ibex (Vivado synthesis)
6m 56s
Large Designs Tests
/
Ibex (F4PGA synthesis)
11m 25s
Large Designs Tests
/
Opentitan 9d82960888 (synthesis)
38m 10s
Large Designs Tests
/
Opentitan (synthesis)
1h 0m
Large Designs Tests
/
VeeR-EH1 (synthesis)
6m 1s
Large Designs Tests
/
Black Parrot (AMD (Xilinx) FPGA synthesis)
16m 43s
Large Designs Tests
/
Black Parrot (ASIC synthesis)
38m 18s
Large Designs Tests
/
Black Parrot (AMD (Xilinx) with PySynlig)
21m 57s
Diff generated BSG Micro Designs tests
/
Parse and diff BSG Micro Designs
6m 46s
Matrix: Formal Verification Tests / tests-formal-verification
Parsing Tests
/
Generate AST diff
2m 4s
Parsing Tests
/
Summary Generation
1m 27s
Verify README Correctness (Download And Run Release)
0s
Annotations
1 error and 7 warnings
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Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)
Process completed with exit code 2.
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Large Designs Tests / VeeR-EH1 (synthesis)
No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.
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Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.
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Formal Verification Tests / yosys
No files were found with the provided path: yosys_formal_verification_logs.tar. No artifacts will be uploaded.
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Formal Verification Tests / simple
No files were found with the provided path: simple_formal_verification_logs.tar. No artifacts will be uploaded.
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Formal Verification Tests / sv2v
No files were found with the provided path: sv2v_formal_verification_logs.tar. No artifacts will be uploaded.
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Large Designs Tests / Black Parrot (ASIC synthesis)
No files were found with the provided path: build
third_party/OpenROAD-flow-scripts/logs
third_party/OpenROAD-flow-scripts/reports
third_party/OpenROAD-flow-scripts/results. No artifacts will be uploaded.
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Large Designs Tests / Opentitan (synthesis)
No files were found with the provided path: tests/build/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1/synth-yosys/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1.edif. No artifacts will be uploaded.
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Artifacts
Produced during runtime
| Name | Size | |
|---|---|---|
|
binaries-asan
|
288 MB |
|
|
binaries-package
|
22.6 MB |
|
|
binaries-plugin
|
40.8 MB |
|
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binaries-pysynlig
|
656 MB |
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binaries-release
|
41.4 MB |
|
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bp_e_bp_unicore_cfg.edif
|
3.9 MB |
|
|
bsg-logs
|
5.47 MB |
|
|
bsg-outputs
|
1.72 MB |
|
|
lowrisc_ibex_top_artya7_surelog_0.1.bit
|
107 KB |
|
|
lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit
|
612 KB |
|
|
opentitan-logs-full
|
5.08 MB |
|
|
opentitan-logs-quick
|
1.52 MB |
|
|
plots_binaries-asan
|
139 KB |
|
|
plots_binaries-package
|
142 KB |
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|
plots_binaries-plugin
|
141 KB |
|
|
plots_binaries-pysynlig
|
169 KB |
|
|
plots_binaries-release
|
143 KB |
|
|
plots_blackparrot_synth_asic
|
222 KB |
|
|
plots_blackparrot_synth_xilinx
|
107 KB |
|
|
plots_blackparrot_synth_xilinx_python
|
130 KB |
|
|
plots_build_tools
|
81.2 KB |
|
|
plots_formal_verification_simple
|
102 KB |
|
|
plots_formal_verification_sv2v
|
120 KB |
|
|
plots_formal_verification_yosys
|
97.7 KB |
|
|
plots_ibex_synth
|
47.7 KB |
|
|
plots_ibex_synth_f4pga
|
79.8 KB |
|
|
plots_opentitan_9d82960888_synth
|
199 KB |
|
|
plots_opentitan_parse_report_full
|
84.4 KB |
|
|
plots_opentitan_parse_report_quick
|
44.8 KB |
|
|
plots_opentitan_synth
|
302 KB |
|
|
plots_tests_asan_read_systemverilog
|
220 KB |
|
|
plots_tests_asan_read_uhdm
|
164 KB |
|
|
plots_tests_plugin_read_systemverilog
|
35.6 KB |
|
|
plots_tests_plugin_read_uhdm
|
34.3 KB |
|
|
plots_tests_release_read_systemverilog
|
36.5 KB |
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plots_tests_release_read_uhdm
|
34.1 KB |
|
|
plots_veer_synth
|
39.2 KB |
|
|
results_parsing_tests_asan_read_systemverilog
Expired
|
389 KB |
|
|
results_parsing_tests_asan_read_uhdm
Expired
|
1.81 MB |
|
|
results_parsing_tests_plugin_read_systemverilog
Expired
|
256 KB |
|
|
results_parsing_tests_plugin_read_uhdm
Expired
|
1.71 MB |
|
|
results_parsing_tests_release_read_systemverilog
Expired
|
255 KB |
|
|
results_parsing_tests_release_read_uhdm
Expired
|
1.7 MB |
|
|
tools
|
38.9 MB |
|
|
top_artya7.bit
|
121 KB |
|