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  1. StitchUp StitchUp Public

    StitchUp is a plugin to the LegUp High Level Synthesis tool that enables the generation of fault tolerant FPGA circuits.

    Coq 9 3

  2. RELISH RELISH Public

    Runahead Execution of Load Instructions via Sliced Hardware (RELISH) -- a High level synthesis optimisation pass, which automatically constructs helper circuits used to prefetch load instructions.

    Verilog 4 1

  3. EmSys EmSys Public

    40 9

  4. OSS-HAL OSS-HAL Public

    A base FPGA image for the OPS-SAT Swansea project

    VHDL 2

  5. sv-tute sv-tute Public

    Tutorials introducing System Verilog using verilator

    Makefile 5 1

  6. verilator-vis verilator-vis Public

    A visualisation framework for Verilator. Contains a collection of javascript libraries and some plumbing code for visualising RTL simulations in Verilator at a high-level. This is a submodule in mo…

    JavaScript 1