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Juan Gonzalez-Gomez edited this page Apr 1, 2024 · 4 revisions

Contents

Usage

apio verify [OPTIONS]

Description

Verify the verilog code. It is agnostic of the FPGA. It does not use the constraint file

Required package: oss-cad-suite

Options

Flag Long Flag Description
-p --project-dir Set the target directory for the project.

Examples

1. Verify the leds example

apio verify


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