input_sequence

Type

Object Array

Default

none - Specification is required!

Description

Specifies the input sequence for initializing the simulation. For each simulation, PROLEAD randomly selects a group and assigns the group value. After initialization, all manually defined signals retain their values until the simulation concludes. During initialization, the user must define all input signals. Input signals can be specified in the following ways:

1. Constants: Every input signal can be set to a constant value such as 1'b0 or 4'h7.
2. Random values: By using the $ notation, the user can provide random constants to the input. For example, 4'h$ sets a 4-bit input vector to a random value. Unlike always_random_inputs, the randomness remains constant until the signal is explicitly changed.
3. Shared values: To assign a share of the group value to a signal, use the group_in signal, followed by the share number and the range of the group value. For example, group_in0[7:0] represents the first share of the first eight bits of the group value.

Impact

The user must provide an input sequence that ensures correct circuit processing. To verify the accuracy of the input sequence, we recommend using the waveform_simulation setting to check some simulations.

Examples

/* Assume that SharedInput is a 16-bit vector that stores two 8-bit input shares*/
"input_sequence": [
{
    /* Specify the first clock cycles */
    "signals": [
        {
            /* Provide the initial input value for the first input share */
            "name": "SharedInput[7:0]",
            "value": "group_in0[7:0]"
        },
        {
            /* Provide the initial input value for the second input share */
            "name": "SharedInput[15:8]",
            "value": "group_in1[7:0]"
        },
        {
            /* Provide a constant input for the reset signal */
            "name": "rst",
            "value": "1'b1"
        }
    ],
    /* Hold the state for two clock cycles */
    "hold_for_cycles": 2
},    
{
    /* Specify the next clock cycle. PROLEAD holds the final input state for the rest of the simulation */
    "signals": [
        /* All inputs which are not changed here stay the same */
        {
            /* Set the reset signal to zero. */
            "name": "rst",
            "value": "1'b0"
        }
    ]
    /* If hold_for_cycles is not specified, it is set to one */
}
]

In this example, we assume that the implementation receives its shared input in a reset state which takes two clock cycles. Afterqrds, the state changes to an evaluation state and keeps its inputs during evaluation.