Synthesis

Synopsis Design Compiler

All examples are based on designs synthesized by NANG45 standard cell library and Synopsis Design Compiler. The following commands (for synthesis script) can be used to restrict the resulting netlist to only those cells which are supported by PROLEAD.

set_dont_use [get_lib_cells NangateOpenCellLibrary/FA*]
set_dont_use [get_lib_cells NangateOpenCellLibrary/HA*]
set_dont_use [get_lib_cells NangateOpenCellLibrary/AOI*]
set_dont_use [get_lib_cells NangateOpenCellLibrary/OAI*]
set_dont_use [get_lib_cells NangateOpenCellLibrary/MUX*]
set_dont_use [get_lib_cells NangateOpenCellLibrary/CLKBUF*]
set_dont_use [get_lib_cells NangateOpenCellLibrary/OR3*]
set_dont_use [get_lib_cells NangateOpenCellLibrary/OR4*]
set_dont_use [get_lib_cells NangateOpenCellLibrary/OR5*]
set_dont_use [get_lib_cells NangateOpenCellLibrary/NOR3*]
set_dont_use [get_lib_cells NangateOpenCellLibrary/NOR4*]
set_dont_use [get_lib_cells NangateOpenCellLibrary/NOR5*]
set_dont_use [get_lib_cells NangateOpenCellLibrary/XNOR3*]
set_dont_use [get_lib_cells NangateOpenCellLibrary/XNOR4*]
set_dont_use [get_lib_cells NangateOpenCellLibrary/XNOR5*]
set_dont_use [get_lib_cells NangateOpenCellLibrary/XOR3*]
set_dont_use [get_lib_cells NangateOpenCellLibrary/XOR4*]
set_dont_use [get_lib_cells NangateOpenCellLibrary/XOR5*]
set_dont_use [get_lib_cells NangateOpenCellLibrary/AND3*]
set_dont_use [get_lib_cells NangateOpenCellLibrary/AND4*]
set_dont_use [get_lib_cells NangateOpenCellLibrary/AND5*]
set_dont_use [get_lib_cells NangateOpenCellLibrary/NAND3*]
set_dont_use [get_lib_cells NangateOpenCellLibrary/NAND4*]
set_dont_use [get_lib_cells NangateOpenCellLibrary/NAND5*]
set_dont_use [get_lib_cells NangateOpenCellLibrary/BUF*]

The following commands can be used to force the synthesizer to compile, keep the hierarchy and make a flattened netlist of the design. PROLEAD can handle flattened and non-flattened netlists. Hence, flattening the netlist is optional.

compile -map_effort medium -area_effort medium # Compile
compile_ultra -no_autoungroup # Keep the hierarchy
ungroup -all -flatten # Flatten netlist (optional)

Yosys

PROLEAD can also parse and evaluate the netlist generated by open-source synthesizer Yosys. The generated netlist should be based on a certain library whose cells are supported by PROLEAD. As reference, we refer to the Yosys directory where an examplary synthesis script (for VHDL and Verilog) in addition to a customized library are given.

For example, if you run synthesize.sh from its directory, the following command leads to the synthesis of the Verilog example Low-Latency Keccak-f[25] with the predefined cell library.

bash synthesize.sh verilog ../../examples/Hardware/KECCAK_Low_Latency_d1/rtl/ keccak_top.v

The same can be done for VHDL examples such as TI, PRESENT S-box, Not uniform.

bash synthesize.sh vhdl ../../examples/Hardware/PRESENT_Sbox_TI_d1_Not_Uniform/rtl/ sharedSbox