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Adding RISC-V Vector support for CHERIoT #58

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Adding RISC-V Vector support for CHERIoT #58

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41734ad
Adding RISC-V Vector support for CHERIoT (no floating point support)
vmurali Jul 10, 2024
dc18c38
Added Vector CSRs into allow-list
vmurali Jul 11, 2024
042811f
Added vector and floating point registers in CSRs depending on extens…
vmurali Jul 22, 2024
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35 changes: 27 additions & 8 deletions Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -31,7 +31,13 @@ SAIL_DEFAULT_INST = $(SAIL_RISCV_MODEL_DIR)/riscv_insts_base.sail \
$(SAIL_CHERI_MODEL_DIR)/cheri_insts_begin.sail \
$(SAIL_CHERI_MODEL_DIR)/cheri_insts.sail \
$(SAIL_CHERI_MODEL_DIR)/cheri_insts_cext.sail \
$(SAIL_CHERI_MODEL_DIR)/cheri_insts_end.sail
$(SAIL_CHERI_MODEL_DIR)/cheri_insts_end.sail \
$(SAIL_RISCV_MODEL_DIR)/riscv_insts_fext.sail \
$(SAIL_RISCV_MODEL_DIR)/riscv_insts_cfext.sail \
$(SAIL_RISCV_MODEL_DIR)/riscv_insts_dext.sail \
$(SAIL_RISCV_MODEL_DIR)/riscv_insts_zfh.sail \
$(SAIL_RISCV_MODEL_DIR)/riscv_insts_zfa.sail \

# $(SAIL_FD_INST) \
# $(SAIL_RISCV_MODEL_DIR)/riscv_insts_aext.sail
SAIL_SEQ_INST = $(SAIL_DEFAULT_INST) $(SAIL_RISCV_MODEL_DIR)/riscv_jalr_seq.sail
Expand All @@ -42,16 +48,29 @@ SAIL_RMEM_INST_SRCS = $(SAIL_RISCV_MODEL_DIR)/riscv_insts_begin.sail $(SAIL_RMEM

# System and platform sources
SAIL_SYS_SRCS += $(SAIL_RISCV_MODEL_DIR)/riscv_next_regs.sail
SAIL_SYS_SRCS += $(SAIL_RISCV_MODEL_DIR)/riscv_vext_control.sail
SAIL_SYS_SRCS += $(SAIL_CHERI_MODEL_DIR)/cheri_sys_exceptions.sail
SAIL_SYS_SRCS += $(SAIL_RISCV_MODEL_DIR)/riscv_sync_exception.sail
SAIL_SYS_SRCS += $(SAIL_RISCV_MODEL_DIR)/riscv_next_control.sail
# SAIL_SYS_SRCS += $(SAIL_RISCV_MODEL_DIR)/riscv_softfloat_interface.sail
# SAIL_SYS_SRCS += $(SAIL_RISCV_MODEL_DIR)/riscv_fdext_regs.sail
# SAIL_SYS_SRCS += $(SAIL_RISCV_MODEL_DIR)/riscv_fdext_control.sail
SAIL_SYS_SRCS += $(SAIL_RISCV_MODEL_DIR)/riscv_softfloat_interface.sail
SAIL_SYS_SRCS += $(SAIL_RISCV_MODEL_DIR)/riscv_fdext_regs.sail
SAIL_SYS_SRCS += $(SAIL_RISCV_MODEL_DIR)/riscv_fdext_control.sail
SAIL_SYS_SRCS += $(SAIL_RISCV_MODEL_DIR)/riscv_csr_ext.sail
SAIL_SYS_SRCS += $(SAIL_RISCV_MODEL_DIR)/riscv_sys_control.sail
SAIL_SYS_SRCS += $(SAIL_CHECK_SRCS)

SAIL_DEFAULT_INST += $(SAIL_RISCV_MODEL_DIR)/riscv_insts_vext_utils.sail
SAIL_DEFAULT_INST += $(SAIL_RISCV_MODEL_DIR)/riscv_insts_vext_fp_utils.sail
SAIL_DEFAULT_INST += $(SAIL_RISCV_MODEL_DIR)/riscv_insts_vext_vset.sail
SAIL_DEFAULT_INST += $(SAIL_RISCV_MODEL_DIR)/riscv_insts_vext_arith.sail
SAIL_DEFAULT_INST += $(SAIL_RISCV_MODEL_DIR)/riscv_insts_vext_fp.sail
SAIL_DEFAULT_INST += $(SAIL_RISCV_MODEL_DIR)/riscv_insts_vext_mem.sail
SAIL_DEFAULT_INST += $(SAIL_RISCV_MODEL_DIR)/riscv_insts_vext_mask.sail
SAIL_DEFAULT_INST += $(SAIL_RISCV_MODEL_DIR)/riscv_insts_vext_vm.sail
SAIL_DEFAULT_INST += $(SAIL_RISCV_MODEL_DIR)/riscv_insts_vext_fp_vm.sail
SAIL_DEFAULT_INST += $(SAIL_RISCV_MODEL_DIR)/riscv_insts_vext_red.sail
SAIL_DEFAULT_INST += $(SAIL_RISCV_MODEL_DIR)/riscv_insts_vext_fp_red.sail

SAIL_RV32_VM_SRCS = $(SAIL_RISCV_MODEL_DIR)/riscv_vmem_sv32.sail \
$(SAIL_RISCV_MODEL_DIR)/riscv_vmem_rv32.sail
SAIL_RV64_VM_SRCS = $(SAIL_RISCV_MODEL_DIR)/riscv_vmem_sv39.sail \
Expand All @@ -74,6 +93,7 @@ PRELUDE = $(SAIL_RISCV_MODEL_DIR)/prelude.sail \
$(SAIL_RISCV_MODEL_DIR)/prelude_mem.sail

SAIL_REGS_SRCS = $(SAIL_CHERI_MODEL_DIR)/cheri_reg_type.sail \
$(SAIL_RISCV_MODEL_DIR)/riscv_freg_type.sail \
$(SAIL_RISCV_MODEL_DIR)/riscv_csr_map.sail \
$(SAIL_CHERI_MODEL_DIR)/cheri_scr_map.sail \
$(SAIL_CHERI_MODEL_DIR)/cheri_vmem_types.sail \
Expand Down Expand Up @@ -168,15 +188,14 @@ BBV_DIR?=../bbv

C_WARNINGS ?=
#-Wall -Wextra -Wno-unused-label -Wno-unused-parameter -Wno-unused-but-set-variable -Wno-unused-function
C_INCS = $(addprefix $(SAIL_RISCV_DIR)/c_emulator/,riscv_prelude.h riscv_platform_impl.h riscv_platform.h)
C_SRCS = $(addprefix $(SAIL_RISCV_DIR)/c_emulator/,riscv_prelude.c riscv_platform_impl.c riscv_platform.c)
C_INCS = $(addprefix $(SAIL_RISCV_DIR)/c_emulator/,riscv_prelude.h riscv_platform_impl.h riscv_platform.h riscv_softfloat.h)
C_SRCS = $(addprefix $(SAIL_RISCV_DIR)/c_emulator/,riscv_prelude.c riscv_platform_impl.c riscv_platform.c riscv_softfloat.c)

SOFTFLOAT_DIR = $(SAIL_RISCV_DIR)/c_emulator/SoftFloat-3e
SOFTFLOAT_INCDIR = $(SOFTFLOAT_DIR)/source/include
SOFTFLOAT_LIBDIR = $(SOFTFLOAT_DIR)/build/Linux-RISCV-GCC
SOFTFLOAT_FLAGS = -I $(SOFTFLOAT_INCDIR)
SOFTFLOAT_LIBS =
#$(SOFTFLOAT_LIBDIR)/softfloat.a
SOFTFLOAT_LIBS = $(SOFTFLOAT_LIBDIR)/softfloat.a
SOFTFLOAT_SPECIALIZE_TYPE = RISCV

GMP_FLAGS = $(shell pkg-config --cflags gmp)
Expand Down
2 changes: 1 addition & 1 deletion sail-riscv
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Submodule sail-riscv updated 7 files
+3 −0 Makefile
+126 −0 model/riscv_insts_vext_fp_red.sail
+663 −0 model/riscv_insts_vext_fp_utils.sail
+142 −0 model/riscv_insts_vext_fp_vm.sail
+0 −113 model/riscv_insts_vext_red.sail
+0 −651 model/riscv_insts_vext_utils.sail
+1 −130 model/riscv_insts_vext_vm.sail
10 changes: 10 additions & 0 deletions src/cheri_addr_checks.sail
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Original file line number Diff line number Diff line change
Expand Up @@ -236,6 +236,16 @@ function ext_check_CSR (csrno : bits(12), p : Privilege, isWrite : bool) -> bool
0xC80 => not(isWrite), // cycleh
0xC81 => not(isWrite), // timeh
0xC82 => not(isWrite), // instreth
0x008 => haveVExt(), // vstart
0x009 => haveVExt(), // vxsat
0x00A => haveVExt(), // vxrm
0x00F => haveVExt(), // vcsr
0xC20 => haveVExt() & not(isWrite), // vl
0xC21 => haveVExt() & not(isWrite), // vtype
0xC22 => haveVExt() & not(isWrite), // vlenb
0x001 => haveFExt() | haveDExt(), // fflags
0x002 => haveFExt() | haveDExt(), // frm
0x003 => haveFExt() | haveDExt(), // fcsr
_ => false
} else {
true
Expand Down