Adding RISC-V Vector support for CHERIoT

[vmurali]

Companion to CHERIoT-Platform/sail-riscv#2

[vmurali]

@rmn30 @nwf-msr

[marnovandermaas]

If I'm not mistaken this adds the vanilla vector extension to CHERIoT Sail. How do we deal with vectorized memory addresses? Is it worth describing the interaction between CHERIoT and the V extension in the ISA document before changing the Sail?

[vmurali]

If you look at, for instance, this, it uses the function ext_data_get_addr that is effectively overwritten in cheriot-sail. So everything works immediately.

[rmn30]

Yes, the memory checks should just work if they follow the conventions of the existing RISC-V memory access instructions. We do need to think about the CSRs though. They probably need to be added to the allow list.

[vmurali]

Good point. I overlooked that. Let me see if that can be fixed.

[vmurali]

Where is the allow list? https://github.com/CHERIoT-Platform/sail-riscv/blob/cf541bea6be2d612c9bc91af032ab277a3756512/model/riscv_csr_map.sail#L171-L177 seems to be uncommented.

[rmn30]

This one for code running without access system regs perm: https://github.com/microsoft/cheriot-sail/blob/09ef3a7daad39293596e06dcf9079194b47f3e8c/src/cheri_addr_checks.sail#L229

[vmurali]

This one for code running without access system regs perm:

https://github.com/microsoft/cheriot-sail/blob/09ef3a7daad39293596e06dcf9079194b47f3e8c/src/cheri_addr_checks.sail#L229

Fixed. Thanks!