FPGA: Add CPU instruction address SPI access control #243
Commits on Jul 4, 2024
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FPGA: Add CPU instruction address SPI access control
Add logic that checks if the CPU is reading an instruction to execute from ROM or not. If instructions are read from ROM, access to the SPI from the API is granted, and signals between the SPI master and a slave are allowed. If instructions are not read from ROM, any API access is blocked. and between the SPI master and a slave are disabled. Signed-off-by: Joachim Strömbergson <[email protected]> -
fpga: block control inputs to SPI-master, not external interface
Signed-off-by: Joachim Strömbergson <[email protected]>
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Commits on Jul 8, 2024
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fpga: Always allow access to SPI-master
Signed-off-by: Joachim Strömbergson <[email protected]>
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fpga: Remove cpu_instr from SPI access control condition
Signed-off-by: Joachim Strömbergson <[email protected]>
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Remove cpu_valid from SPI access control condition
Signed-off-by: Joachim Strömbergson <[email protected]>
Commits on Jul 9, 2024
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fpga: Add stateful access control
Add access stateful control register that toggles if access to a resources is granted based on if code is excuted from ROM or RAM. The register is used to enable or block access to SPI but potentially other HW resources. Signed-off-by: Joachim Strömbergson <[email protected]> -
Use the access_ok_reg, not obsolete spi_acces_ok wire Remove now obsolete ROM_PREFIX define Signed-off-by: Joachim Strömbergson <[email protected]> -
fpga: Include SPI master during linting
Signed-off-by: Joachim Strömbergson <[email protected]>
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fpga: Apply access_ok_reg on API reads
Signed-off-by: Joachim Strömbergson <[email protected]>
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fpga: Add testcase for access control
Signed-off-by: Joachim Strömbergson <[email protected]>
Commits on Jul 10, 2024
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fpga: Add API to enable and disable SPI access
Signed-off-by: Joachim Strömbergson <[email protected]>
Commits on Jul 11, 2024
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fpga: Add new SPI access control logis
New logic looks at instruction execution from a defined trampoline address to enable stateful SPI access. The access is disabled as soon as an instruction is executed from any address in RAM. Signed-off-by: Joachim Strömbergson <[email protected]> -
fpga: Add testcase for SPI access control
Add testcase that checks that access control is enabled and disabled as expected. Signed-off-by: Joachim Strömbergson <[email protected]>