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FPGA: Format verilog code
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@jthornblad @dehanj
jthornblad authored and dehanj committed Oct 22, 2024
1 parent e04aacd commit 3514d7e
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109 changes: 56 additions & 53 deletions hw/application_fpga/core/clk_reset_gen/rtl/clk_reset_gen.v
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Original file line number Diff line number Diff line change
Expand Up @@ -16,33 +16,34 @@

`default_nettype none

module clk_reset_gen #(parameter RESET_CYCLES = 200)
(
input wire sys_reset,
module clk_reset_gen #(
parameter RESET_CYCLES = 200
) (
input wire sys_reset,

output wire clk,
output wire rst_n
);
output wire clk,
output wire rst_n
);


//----------------------------------------------------------------
// Registers with associated wires.
//----------------------------------------------------------------
reg [7 : 0] rst_ctr_reg = 8'h0;
reg [7 : 0] rst_ctr_new;
reg rst_ctr_we;
reg [7 : 0] rst_ctr_reg = 8'h0;
reg [7 : 0] rst_ctr_new;
reg rst_ctr_we;

reg rst_n_reg = 1'h0;
reg rst_n_new;
reg rst_n_reg = 1'h0;
reg rst_n_new;

reg sys_reset_reg;
reg sys_reset_reg;


//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
wire hfosc_clk;
wire pll_clk;
wire hfosc_clk;
wire pll_clk;


//----------------------------------------------------------------
Expand All @@ -58,8 +59,13 @@ module clk_reset_gen #(parameter RESET_CYCLES = 200)

// Use the FPGA internal High Frequency OSCillator as clock source.
// 00: 48MHz, 01: 24MHz, 10: 12MHz, 11: 6MHz
SB_HFOSC #(.CLKHF_DIV("0b10")
) hfosc_inst (.CLKHFPU(1'b1),.CLKHFEN(1'b1),.CLKHF(hfosc_clk));
SB_HFOSC #(
.CLKHF_DIV("0b10")
) hfosc_inst (
.CLKHFPU(1'b1),
.CLKHFEN(1'b1),
.CLKHF (hfosc_clk)
);


// Use a PLL to generate a new clock frequency based on the HFOSC clock.
Expand All @@ -74,63 +80,60 @@ module clk_reset_gen #(parameter RESET_CYCLES = 200)
//
// (12000000 * (55 + 1)) / (2^5 * (0 + 1)) = 21000000
SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"),
.DIVR(4'd0), // DIVR = 0
.DIVF(7'd55), // DIVF = 55
.DIVQ(3'd5), // DIVQ = 5
.FILTER_RANGE(3'b001) // FILTER_RANGE = 1
) pll_inst (
.RESETB(1'b1),
.BYPASS(1'b0),
.REFERENCECLK(hfosc_clk),
.PLLOUTCORE(pll_clk)
);
.FEEDBACK_PATH("SIMPLE"),
.DIVR(4'd0), // DIVR = 0
.DIVF(7'd55), // DIVF = 55
.DIVQ(3'd5), // DIVQ = 5
.FILTER_RANGE(3'b001) // FILTER_RANGE = 1
) pll_inst (
.RESETB(1'b1),
.BYPASS(1'b0),
.REFERENCECLK(hfosc_clk),
.PLLOUTCORE(pll_clk)
);


// Use a Global Buffer to distribute the clock.
SB_GB gb_inst (
.USER_SIGNAL_TO_GLOBAL_BUFFER (pll_clk),
.GLOBAL_BUFFER_OUTPUT (clk)
);
.USER_SIGNAL_TO_GLOBAL_BUFFER(pll_clk),
.GLOBAL_BUFFER_OUTPUT(clk)
);

/* verilator lint_on PINMISSING */


//----------------------------------------------------------------
// reg_update.
//----------------------------------------------------------------
always @(posedge clk)
begin : reg_update
rst_n_reg <= rst_n_new;
sys_reset_reg <= sys_reset;
always @(posedge clk) begin : reg_update
rst_n_reg <= rst_n_new;
sys_reset_reg <= sys_reset;

if (rst_ctr_we)
rst_ctr_reg <= rst_ctr_new;
end
if (rst_ctr_we) rst_ctr_reg <= rst_ctr_new;
end


//----------------------------------------------------------------
// rst_logic.
//----------------------------------------------------------------
always @*
begin : rst_logic
rst_n_new = 1'h1;
always @* begin : rst_logic
rst_n_new = 1'h1;
rst_ctr_new = 8'h0;
rst_ctr_we = 1'h0;

if (sys_reset_reg) begin
rst_ctr_new = 8'h0;
rst_ctr_we = 1'h0;

if (sys_reset_reg) begin
rst_ctr_new = 8'h0;
rst_ctr_we = 1'h1;
end

else if (rst_ctr_reg < RESET_CYCLES) begin
rst_n_new = 1'h0;
rst_ctr_new = rst_ctr_reg + 1'h1;
rst_ctr_we = 1'h1;
end
rst_ctr_we = 1'h1;
end

else if (rst_ctr_reg < RESET_CYCLES) begin
rst_n_new = 1'h0;
rst_ctr_new = rst_ctr_reg + 1'h1;
rst_ctr_we = 1'h1;
end
end

endmodule // reset_gen
endmodule // reset_gen

//======================================================================
// EOF reset_gen.v
Expand Down
194 changes: 96 additions & 98 deletions hw/application_fpga/core/fw_ram/rtl/fw_ram.v
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Original file line number Diff line number Diff line change
Expand Up @@ -13,31 +13,31 @@

`default_nettype none

module fw_ram(
input wire clk,
input wire reset_n,
module fw_ram (
input wire clk,
input wire reset_n,

input wire fw_app_mode,
input wire fw_app_mode,

input wire cs,
input wire [3 : 0] we,
input wire [8 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data,
output wire ready
);
input wire cs,
input wire [ 3 : 0] we,
input wire [ 8 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data,
output wire ready
);


//----------------------------------------------------------------
// Registers and wires.
//----------------------------------------------------------------
reg [31 : 0] tmp_read_data;
reg [31 : 0] mem_read_data0;
reg [31 : 0] mem_read_data1;
reg ready_reg;
wire fw_app_cs;
reg bank0;
reg bank1;
reg [31 : 0] tmp_read_data;
reg [31 : 0] mem_read_data0;
reg [31 : 0] mem_read_data1;
reg ready_reg;
wire fw_app_cs;
reg bank0;
reg bank1;


//----------------------------------------------------------------
Expand All @@ -51,99 +51,97 @@ module fw_ram(
//----------------------------------------------------------------
// Block RAM instances.
//----------------------------------------------------------------
SB_RAM40_4K fw_ram0_0(
.RDATA(mem_read_data0[15 : 0]),
.RADDR({3'h0, address[7 : 0]}),
.RCLK(clk),
.RCLKE(1'h1),
.RE(fw_app_cs & bank0),
.WADDR({3'h0, address[7 : 0]}),
.WCLK(clk),
.WCLKE(1'h1),
.WDATA(write_data[15 : 0]),
.WE((|we & fw_app_cs & bank0)),
.MASK({{8{~we[1]}}, {8{~we[0]}}})
);

SB_RAM40_4K fw_ram0_1(
.RDATA(mem_read_data0[31 : 16]),
.RADDR({3'h0, address[7 : 0]}),
.RCLK(clk),
.RCLKE(1'h1),
.RE(fw_app_cs & bank0),
.WADDR({3'h0, address[7 : 0]}),
.WCLK(clk),
.WCLKE(1'h1),
.WDATA(write_data[31 : 16]),
.WE((|we & fw_app_cs & bank0)),
.MASK({{8{~we[3]}}, {8{~we[2]}}})
);


SB_RAM40_4K fw_ram1_0(
.RDATA(mem_read_data1[15 : 0]),
.RADDR({3'h0, address[7 : 0]}),
.RCLK(clk),
.RCLKE(1'h1),
.RE(fw_app_cs & bank1),
.WADDR({3'h0, address[7 : 0]}),
.WCLK(clk),
.WCLKE(1'h1),
.WDATA(write_data[15 : 0]),
.WE((|we & fw_app_cs & bank1)),
.MASK({{8{~we[1]}}, {8{~we[0]}}})
);

SB_RAM40_4K fw_ram1_1(
.RDATA(mem_read_data1[31 : 16]),
.RADDR({3'h0, address[7 : 0]}),
.RCLK(clk),
.RCLKE(1'h1),
.RE(fw_app_cs & bank1),
.WADDR({3'h0, address[7 : 0]}),
.WCLK(clk),
.WCLKE(1'h1),
.WDATA(write_data[31 : 16]),
.WE((|we & fw_app_cs & bank1)),
.MASK({{8{~we[3]}}, {8{~we[2]}}})
);
SB_RAM40_4K fw_ram0_0 (
.RDATA(mem_read_data0[15 : 0]),
.RADDR({3'h0, address[7 : 0]}),
.RCLK(clk),
.RCLKE(1'h1),
.RE(fw_app_cs & bank0),
.WADDR({3'h0, address[7 : 0]}),
.WCLK(clk),
.WCLKE(1'h1),
.WDATA(write_data[15 : 0]),
.WE((|we & fw_app_cs & bank0)),
.MASK({{8{~we[1]}}, {8{~we[0]}}})
);

SB_RAM40_4K fw_ram0_1 (
.RDATA(mem_read_data0[31 : 16]),
.RADDR({3'h0, address[7 : 0]}),
.RCLK(clk),
.RCLKE(1'h1),
.RE(fw_app_cs & bank0),
.WADDR({3'h0, address[7 : 0]}),
.WCLK(clk),
.WCLKE(1'h1),
.WDATA(write_data[31 : 16]),
.WE((|we & fw_app_cs & bank0)),
.MASK({{8{~we[3]}}, {8{~we[2]}}})
);


SB_RAM40_4K fw_ram1_0 (
.RDATA(mem_read_data1[15 : 0]),
.RADDR({3'h0, address[7 : 0]}),
.RCLK(clk),
.RCLKE(1'h1),
.RE(fw_app_cs & bank1),
.WADDR({3'h0, address[7 : 0]}),
.WCLK(clk),
.WCLKE(1'h1),
.WDATA(write_data[15 : 0]),
.WE((|we & fw_app_cs & bank1)),
.MASK({{8{~we[1]}}, {8{~we[0]}}})
);

SB_RAM40_4K fw_ram1_1 (
.RDATA(mem_read_data1[31 : 16]),
.RADDR({3'h0, address[7 : 0]}),
.RCLK(clk),
.RCLKE(1'h1),
.RE(fw_app_cs & bank1),
.WADDR({3'h0, address[7 : 0]}),
.WCLK(clk),
.WCLKE(1'h1),
.WDATA(write_data[31 : 16]),
.WE((|we & fw_app_cs & bank1)),
.MASK({{8{~we[3]}}, {8{~we[2]}}})
);

//----------------------------------------------------------------
// reg_update
//----------------------------------------------------------------
always @(posedge clk)
begin : reg_update
if (!reset_n) begin
ready_reg <= 1'h0;
end
else begin
ready_reg <= cs;
end
always @(posedge clk) begin : reg_update
if (!reset_n) begin
ready_reg <= 1'h0;
end
else begin
ready_reg <= cs;
end
end


//----------------------------------------------------------------
// rw_mux
//----------------------------------------------------------------
always @*
begin : rw_mux;
bank0 = 1'h0;
bank1 = 1'h0;
tmp_read_data = 32'h0;

if (fw_app_cs) begin
if (address[8]) begin
bank1 = 1'h1;
tmp_read_data = mem_read_data1;
end
else begin
bank0 = 1'h1;
tmp_read_data = mem_read_data0;
end
always @* begin : rw_mux
bank0 = 1'h0;
bank1 = 1'h0;
tmp_read_data = 32'h0;

if (fw_app_cs) begin
if (address[8]) begin
bank1 = 1'h1;
tmp_read_data = mem_read_data1;
end
else begin
bank0 = 1'h1;
tmp_read_data = mem_read_data0;
end
end
end

endmodule // fw_ram
endmodule // fw_ram

//======================================================================
// EOF fw_ram.v
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