FPGA: Add CPU instruction address SPI access control #439
ci.yaml
on: pull_request
build-bitstream
2m 44s
check-firmware
59s
check-verilog
54s
build-other-firmwares
1m 12s
build-spi-bitstream
2m 44s
check-hashes
58s
Annotations
2 errors
check-verilog
Process completed with exit code 2.
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check-hashes
Process completed with exit code 2.
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