Skip to content

FPGA: Add CPU instruction address SPI access control #439

FPGA: Add CPU instruction address SPI access control

FPGA: Add CPU instruction address SPI access control #439

Triggered via pull request July 9, 2024 11:11
Status Failure
Total duration 3m 57s
Artifacts

ci.yaml

on: pull_request
build-bitstream
2m 44s
build-bitstream
check-firmware
59s
check-firmware
check-verilog
54s
check-verilog
build-other-firmwares
1m 12s
build-other-firmwares
build-spi-bitstream
2m 44s
build-spi-bitstream
check-hashes
58s
check-hashes
Fit to window
Zoom out
Zoom in

Annotations

2 errors
check-verilog
Process completed with exit code 2.
check-hashes
Process completed with exit code 2.