FPGA: Add CPU instruction address SPI access control #436

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Triggered via pull request July 9, 2024 10:43

dehanj

synchronize #243

pc_based_access_control_spi

Status Failure

Total duration 5m 31s

Artifacts –

ci.yaml

on: pull_request

build-bitstream

build-other-firmwares

build-spi-bitstream

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3 errors

check-verilog

Process completed with exit code 2.

build-spi-bitstream

Unhandled error: HttpError: Not Found

check-hashes

Process completed with exit code 2.