FPGA: Add CPU instruction address SPI access control #432
dehanjci.yaml
on: pull_request
build-bitstream
3m 40s
check-firmware
1m 12s
check-verilog
1m 16s
build-other-firmwares
1m 3s
build-spi-bitstream
58s
check-hashes
1m 0s
Annotations
3 errors
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build-spi-bitstream
Process completed with exit code 2.
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check-verilog
Process completed with exit code 2.
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check-hashes
Process completed with exit code 2.
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