FPGA: Add CPU instruction address SPI access control #431

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Triggered via pull request July 9, 2024 09:36

dehanj

synchronize #243

pc_based_access_control_spi

Status Failure

Total duration 4m 59s

Artifacts –

ci.yaml

on: pull_request

build-bitstream

build-other-firmwares

build-spi-bitstream

Annotations

4 errors

check-verilog

Process completed with exit code 2.

build-spi-bitstream

Unable to process file command 'env' successfully.

build-spi-bitstream

Invalid format 'Info: Max frequency for clock 'clk': 23.36 MHz (PASS at 18.00 MHz)'

check-hashes

Process completed with exit code 2.