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FPGA: Add CPU instruction address SPI access control #425

FPGA: Add CPU instruction address SPI access control

FPGA: Add CPU instruction address SPI access control #425

Triggered via pull request July 8, 2024 12:49
Status Failure
Total duration 5m 4s
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ci.yaml

on: pull_request
build-bitstream
3m 32s
build-bitstream
check-firmware
56s
check-firmware
check-verilog
55s
check-verilog
build-other-firmwares
1m 0s
build-other-firmwares
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2 errors
check-verilog
Process completed with exit code 2.
check-hashes
Process completed with exit code 2.