Added VOS0 support for stm32h7a3/7b3/7b0

Cargo.toml

@@ -153,7 +153,7 @@ required-features = ["rt", "rm0433"]
 
 [[example]]
 name = "vos0"
-required-features = ["revision_v", "rm0433"]
+required-features = ["revision_v"]
 
 [[example]]
 name = "fmc"

examples/vos0.rs

@@ -1,3 +1,6 @@
+//! Example that demonstrates the use of VOS0
+//!
+//! 7b3/7a3/7b0 support tested on a NUCLEO-H7A3ZI-Q board
 #![deny(warnings)]
 #![no_main]
 #![no_std]
@@ -20,12 +23,17 @@ fn main() -> ! {
     let pwrcfg = example_power!(pwr).vos0(&dp.SYSCFG).freeze();
 
     // Constrain and Freeze clock
-    // The PllConfigStrategy::Normal strategy uses the medium range VCO which has a maximum of 420 Mhz
-    // Switching to PllConfigStrategy::Iterative sets the VCO to wide range to allow this clock to reach 480 Mhz
+    //
+    // The PllConfigStrategy::Normal strategy uses the medium range VCO which
+    // has a maximum of 420 MHz.  Switching to PllConfigStrategy::Iterative sets
+    // the VCO to wide range to allow this clock to reach 480 MHz
     info!("Setup RCC...                  ");
     let rcc = dp.RCC.constrain();
+    #[cfg(not(feature = "rm0455"))]
+    let rcc = rcc.sys_ck(480.MHz());
+    #[cfg(feature = "rm0455")] // 7b3/7a3/7b0 parts are limited to 280MHz
+    let rcc = rcc.sys_ck(280.MHz());
     let ccdr = rcc
-        .sys_ck(480.MHz())
         .pll1_strategy(rcc::PllConfigStrategy::Iterative)
         .freeze(pwrcfg, &dp.SYSCFG);
 
@@ -35,11 +43,17 @@ fn main() -> ! {
 
     // HCLK
     info!("hclk = {} MHz", ccdr.clocks.hclk().raw() as f32 / 1e6);
+    #[cfg(not(feature = "rm0455"))]
     assert_eq!(ccdr.clocks.hclk().raw(), 240_000_000);
+    #[cfg(feature = "rm0455")] // 7b3/7a3/7b0 parts
+    assert_eq!(ccdr.clocks.hclk().raw(), 280_000_000);
 
     // SYS_CK
     info!("sys_ck = {} MHz", ccdr.clocks.sys_ck().raw() as f32 / 1e6);
+    #[cfg(not(feature = "rm0455"))]
     assert_eq!(ccdr.clocks.sys_ck().raw(), 480_000_000);
+    #[cfg(feature = "rm0455")] // 7b3/7a3/7b0 parts
+    assert_eq!(ccdr.clocks.sys_ck().raw(), 280_000_000);
 
     loop {
         cortex_m::asm::nop()

src/pwr.rs

@@ -61,7 +61,7 @@
 //! | --- | --- | ---
 //! | stm32h742/743/753/750 | RM0433 | 480MHz [^revv]
 //! | stm32h745/747/755/757 | RM0399 | 480MHz
-//! | stm32h7a3/7b3/7b0 | RM0455 | VOS0 not supported
+//! | stm32h7a3/7b3/7b0 | RM0455 | 280MHz
 //! | stm32h723/725/730/733/735 | RM0468 | 520MHz [^rm0468ecc]
 //!
 //! [^revv]: Revision V and later parts only
@@ -72,7 +72,10 @@
 
 use crate::rcc::backup::BackupREC;
 use crate::stm32::PWR;
-#[cfg(all(feature = "revision_v", feature = "rm0468"))]
+#[cfg(all(
+    feature = "revision_v",
+    any(feature = "rm0468", feature = "rm0455")
+))]
 use crate::stm32::SYSCFG;
 #[cfg(all(
     feature = "revision_v",
@@ -393,7 +396,12 @@
 
     #[cfg(all(
         feature = "revision_v",
-        any(feature = "rm0433", feature = "rm0399", feature = "rm0468")
+        any(
+            feature = "rm0433",
+            feature = "rm0399",
+            feature = "rm0468",
+            feature = "rm0455"
+        )
     ))]
     #[must_use]
     pub fn vos0(mut self, _: &SYSCFG) -> Self {
@@ -502,10 +510,10 @@
         ))]
         if matches!(self.target_vos, VoltageScale::Scale0) {
             unsafe {
                 &(*RCC::ptr()).apb4enr.modify(|_, w| w.syscfgen().enabled())
             };
             unsafe {
                 &(*SYSCFG::ptr()).pwrcr.modify(|_, w| w.oden().set_bit())
             };
             while d3cr!(self.rb).read().vosrdy().bit_is_clear() {}
             vos = VoltageScale::Scale0;
@@ -524,6 +532,15 @@
             while self.rb.csr1.read().actvosrdy().bit_is_clear() {}
         }
 
+        #[cfg(all(feature = "revision_v", feature = "rm0455"))]
+        if matches!(self.target_vos, VoltageScale::Scale0) {
+            // RM0455 section 6.8.6 says that CSR1.ACTVOSRDY must be set,
+            // before VOS0 can be changed.
+            while self.rb.csr1.read().actvosrdy().bit_is_clear() {}
+            vos = VoltageScale::Scale0;
+            self.voltage_scaling_transition(vos);
+        }
+
         // Disable backup power domain write protection
         self.rb.cr1.modify(|_, w| w.dbp().set_bit());
         while self.rb.cr1.read().dbp().bit_is_clear() {}