squash commit

add stream methods to set pincos, circ and pfctrl

make Stream use dmaDirection instead generic direction

make streams use a new DmaChannel enum instead generic stuff

conditionnel compilation for DmaChannel enum

Redesign ISR API of Stream, this break transfer

redesign Stream trait API, break even more stuff

implement Stream trait, many thing still broken

fix most compile error in Transfer struct

handle DmaDataSize relatd stuff

stream_disable utility function

use utility function for gracefully disable the transfer

add/fix interrupt flag manipulation throught transfer type

fix Bits impl for PeeripeheralIncrmentOffset

fix bit impl of DmaFlowcontreoller

fix missing unsafe section

fix i2c dma to handle transfer API change.

use Dmaflag for more expressive API

dma common interrupts setter & getter

fix spi-dma example

fix rtic-spi-slave-dma.rs example

fix bad link in the doc

add number_of_transfer method on Transfer

fix an example

examples/rtic-serial-dma-rx-idle.rs

@@ -15,7 +15,7 @@ mod app {
 
     use hal::{
         dma::{
-            config::DmaConfig, traits::Stream, traits::StreamISR, PeripheralToMemory, Stream2,
+            config::DmaConfig, PeripheralToMemory, Stream2,
             StreamsTuple, Transfer,
         },
         pac::{DMA2, USART1},
@@ -120,7 +120,7 @@ mod app {
 
         if transfer.is_idle() {
             // Calc received bytes count
-            let bytes_count = BUFFER_SIZE - Stream2::<DMA2>::get_number_of_transfers() as usize;
+            let bytes_count = BUFFER_SIZE - transfer.number_of_transfers() as usize;
 
             // Allocate new buffer
             let new_buffer = cx.local.rx_buffer.take().unwrap();
@@ -143,11 +143,11 @@ mod app {
     fn dma2_stream2(mut cx: dma2_stream2::Context) {
         let transfer = &mut cx.shared.rx_transfer;
 
-        if Stream2::<DMA2>::get_fifo_error_flag() {
-            transfer.clear_fifo_error_interrupt();
+        if transfer.fifo_error_flag() {
+            transfer.clear_fifo_error_flag();
         }
-        if Stream2::<DMA2>::get_transfer_complete_flag() {
-            transfer.clear_transfer_complete_interrupt();
+        if transfer.transfer_complete_flag() {
+            transfer.clear_transfer_complete_flag();
 
             // Buffer is full, but no IDLE received!
             // You can process this data or discard data (ignore transfer complete interrupt and wait IDLE).

examples/rtic-spi-slave-dma.rs

@@ -9,7 +9,7 @@ mod app {
     use embedded_hal::spi::{Mode, Phase, Polarity};
     use hal::{
         dma::{
-            config::DmaConfig, traits::StreamISR, MemoryToPeripheral, PeripheralToMemory, Stream0,
+            config::DmaConfig, MemoryToPeripheral, PeripheralToMemory, Stream0,
             Stream5, StreamsTuple, Transfer,
         },
         gpio::{gpioc::PC13, GpioExt, Output, PushPull},
@@ -138,50 +138,48 @@ mod app {
     // The led lights up if the first byte we receive is a 1, it turns off otherwise
     #[task(binds = DMA1_STREAM0, shared = [rx_transfer, led], local = [rx_buffer])]
     fn on_receiving(cx: on_receiving::Context) {
-        let on_receiving::Context { mut shared, local } = cx;
-        if Stream0::<DMA1>::get_fifo_error_flag() {
-            shared
-                .rx_transfer
-                .lock(|spi_dma| spi_dma.clear_fifo_error_interrupt());
-        }
-        if Stream0::<DMA1>::get_transfer_complete_flag() {
-            shared
-                .rx_transfer
-                .lock(|spi_dma| spi_dma.clear_transfer_complete_interrupt());
-            let filled_buffer = shared.rx_transfer.lock(|spi_dma| {
-                let (result, _) = spi_dma
-                    .next_transfer(local.rx_buffer.take().unwrap())
-                    .unwrap();
-                result
-            });
-            match filled_buffer[0] {
-                1 => shared.led.lock(|led| led.set_low()),
-                _ => shared.led.lock(|led| led.set_high()),
+        let mut rx_transfer = cx.shared.rx_transfer;
+        let mut led = cx.shared.led;
+        let rx_buffer = cx.local.rx_buffer;
+        rx_transfer.lock(|transfer| {
+
+            if transfer.fifo_error_flag() {
+                    transfer.clear_fifo_error_flag();
+            }
+            if transfer.transfer_complete_flag() {
+                transfer.clear_transfer_complete_flag();
+
+                let (filled_buffer,_) = 
+                   transfer 
+                        .next_transfer(rx_buffer.take().unwrap())
+                        .unwrap();
+                match filled_buffer[0] {
+                    1 => led.lock(|led| led.set_low()),
+                    _ => led.lock(|led| led.set_high()),
+                }
+                *rx_buffer = Some(filled_buffer);
             }
-            *local.rx_buffer = Some(filled_buffer);
-        }
+        });
     }
 
     // We either send [1,2,3] or [4,5,6] depending on which buffer was loaded
-    #[task(binds = DMA1_STREAM5, shared = [tx_transfer, led], local = [tx_buffer])]
+    #[task(binds = DMA1_STREAM5, shared = [tx_transfer], local = [tx_buffer])]
     fn on_sending(cx: on_sending::Context) {
-        let on_sending::Context { mut shared, local } = cx;
-        if Stream5::<DMA1>::get_fifo_error_flag() {
-            shared
-                .tx_transfer
-                .lock(|spi_dma| spi_dma.clear_fifo_error_interrupt());
-        }
-        if Stream5::<DMA1>::get_transfer_complete_flag() {
-            shared
-                .tx_transfer
-                .lock(|spi_dma| spi_dma.clear_transfer_complete_interrupt());
-            let filled_buffer = shared.tx_transfer.lock(|spi_dma| {
-                let (result, _) = spi_dma
-                    .next_transfer(local.tx_buffer.take().unwrap())
-                    .unwrap();
-                result
-            });
-            *local.tx_buffer = Some(filled_buffer);
-        }
+        let mut tx_transfer = cx.shared.tx_transfer;
+        let tx_buffer = cx.local.tx_buffer;
+        tx_transfer.lock(|transfer| {
+
+            if transfer.fifo_error_flag() {
+                    transfer.clear_fifo_error_flag();
+            }
+            if transfer.transfer_complete_flag() {
+                    transfer.clear_transfer_complete_flag();
+                let (filled_buffer, _) = 
+                   transfer 
+                        .next_transfer(tx_buffer.take().unwrap())
+                        .unwrap();
+                *tx_buffer = Some(filled_buffer);
+            }
+        });
     }
 }

examples/spi-dma.rs

@@ -10,7 +10,7 @@ use cortex_m_rt::entry;
 use embedded_hal::spi::{Mode, Phase, Polarity};
 use stm32f4xx_hal::pac::interrupt;
 use stm32f4xx_hal::{
-    dma::{config, traits::StreamISR, MemoryToPeripheral, Stream4, StreamsTuple, Transfer},
+    dma::{config, MemoryToPeripheral, Stream4, StreamsTuple, Transfer},
     gpio::Speed,
     pac,
     prelude::*,
@@ -101,11 +101,11 @@ fn DMA2_STREAM4() {
     });
 
     // Its important to clear fifo errors as the transfer is paused until it is cleared
-    if Stream4::<pac::DMA1>::get_fifo_error_flag() {
-        transfer.clear_fifo_error_interrupt();
+    if transfer.fifo_error_flag() {
+        transfer.clear_fifo_error_flag();
     }
-    if Stream4::<pac::DMA1>::get_transfer_complete_flag() {
-        transfer.clear_transfer_complete_interrupt();
+    if transfer.transfer_complete_flag() {
+        transfer.clear_transfer_complete_flag();
         unsafe {
             static mut BUFFER: [u8; ARRAY_SIZE] = [0; ARRAY_SIZE];
             for (i, b) in BUFFER.iter_mut().enumerate() {