use bitflags for DmaFlags, DmaCommonInterrupts and other flags and ev…

…ents

CHANGELOG.md

@@ -8,8 +8,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ## [Unreleased]
 
 - complete and rework Dma Stream API [#666]
+- Use `enumflags2::BitFlags` for interrupt flags and events [#673]
 
 [#666]: https://github.com/stm32-rs/stm32f4xx-hal/pull/666
+[#673]: https://github.com/stm32-rs/stm32f4xx-hal/pull/673
 
 ## [v0.17.1] - 2023-07-24
 
@@ -20,7 +22,6 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ### Fixed
 
 - reset timer interrupt in `Counter::start` [#670]
-
 [#670]: https://github.com/stm32-rs/stm32f4xx-hal/pull/670
 [#671]: https://github.com/stm32-rs/stm32f4xx-hal/pull/671
 

Cargo.toml

@@ -46,7 +46,7 @@ fugit = "0.3.6"
 fugit-timer = "0.1.3"
 rtic-monotonic = { version = "1.0", optional = true }
 systick-monotonic = { version = "1.0", optional = true }
-bitflags = "2.2"
+enumflags2 = "0.7.7"
 embedded-storage = "0.2"
 
 [dependencies.time]

examples/analog-stopwatch-with-spi-ssd1306.rs

@@ -15,8 +15,8 @@ use crate::hal::{
     interrupt, pac,
     prelude::*,
     rcc::{Clocks, Rcc},
-    spi::Spi,
-    timer::{CounterUs, Event, FTimer, Timer},
+    spi::{Mode, Phase, Polarity, Spi},
+    timer::{CounterUs, Event, FTimer, Flag, Timer},
 };
 
 use core::cell::{Cell, RefCell};
@@ -25,8 +25,6 @@ use core::ops::DerefMut;
 use cortex_m::interrupt::{free, CriticalSection, Mutex};
 use heapless::String;
 
-use hal::spi::{Mode, Phase, Polarity};
-
 use core::f32::consts::{FRAC_PI_2, PI};
 use cortex_m_rt::{entry, exception, ExceptionFrame};
 use embedded_graphics::{
@@ -263,7 +261,7 @@ fn EXTI0() {
 fn TIM2() {
     free(|cs| {
         if let Some(ref mut tim2) = TIMER_TIM2.borrow(cs).borrow_mut().deref_mut() {
-            tim2.clear_interrupt(Event::Update);
+            tim2.clear_flags(Flag::Update);
         }
 
         let cell = ELAPSED_MS.borrow(cs);

examples/rtic-serial-dma-rx-idle.rs

@@ -14,7 +14,7 @@
 mod app {
 
     use hal::{
-        dma::{config::DmaConfig, PeripheralToMemory, Stream2, StreamsTuple, Transfer},
+        dma::{config::DmaConfig, DmaFlag, PeripheralToMemory, Stream2, StreamsTuple, Transfer},
         pac::{DMA2, USART1},
         prelude::*,
         rcc::RccExt,
@@ -140,12 +140,9 @@ mod app {
     fn dma2_stream2(mut cx: dma2_stream2::Context) {
         let transfer = &mut cx.shared.rx_transfer;
 
-        if transfer.is_fifo_error() {
-            transfer.clear_fifo_error();
-        }
-        if transfer.is_transfer_complete() {
-            transfer.clear_transfer_complete();
-
+        let flags = transfer.flags();
+        transfer.clear_flags(DmaFlag::FifoError | DmaFlag::TransferComplete);
+        if flags.is_transfer_complete() {
             // Buffer is full, but no IDLE received!
             // You can process this data or discard data (ignore transfer complete interrupt and wait IDLE).
 

examples/rtic-spi-slave-dma.rs

@@ -9,7 +9,7 @@ mod app {
     use embedded_hal::spi::{Mode, Phase, Polarity};
     use hal::{
         dma::{
-            config::DmaConfig, MemoryToPeripheral, PeripheralToMemory, Stream0, Stream5,
+            config::DmaConfig, DmaFlag, MemoryToPeripheral, PeripheralToMemory, Stream0, Stream5,
             StreamsTuple, Transfer,
         },
         gpio::{gpioc::PC13, GpioExt, Output, PushPull},
@@ -142,12 +142,9 @@ mod app {
         let mut led = cx.shared.led;
         let rx_buffer = cx.local.rx_buffer;
         rx_transfer.lock(|transfer| {
-            if transfer.is_fifo_error() {
-                transfer.clear_fifo_error();
-            }
-            if transfer.is_transfer_complete() {
-                transfer.clear_transfer_complete();
-
+            let flags = transfer.flags();
+            transfer.clear_flags(DmaFlag::FifoError | DmaFlag::TransferComplete);
+            if flags.is_transfer_complete() {
                 let (filled_buffer, _) = transfer.next_transfer(rx_buffer.take().unwrap()).unwrap();
                 match filled_buffer[0] {
                     1 => led.lock(|led| led.set_low()),
@@ -164,11 +161,9 @@ mod app {
         let mut tx_transfer = cx.shared.tx_transfer;
         let tx_buffer = cx.local.tx_buffer;
         tx_transfer.lock(|transfer| {
-            if transfer.is_fifo_error() {
-                transfer.clear_fifo_error();
-            }
-            if transfer.is_transfer_complete() {
-                transfer.clear_transfer_complete();
+            let flags = transfer.flags();
+            transfer.clear_flags(DmaFlag::FifoError | DmaFlag::TransferComplete);
+            if flags.is_transfer_complete() {
                 let (filled_buffer, _) = transfer.next_transfer(tx_buffer.take().unwrap()).unwrap();
                 *tx_buffer = Some(filled_buffer);
             }

examples/spi-dma.rs

@@ -3,6 +3,7 @@
 
 // Halt on panic
 use panic_halt as _;
+use stm32f4xx_hal::dma::DmaFlag;
 
 use core::cell::RefCell;
 use cortex_m::interrupt::Mutex;
@@ -100,12 +101,10 @@ fn DMA2_STREAM4() {
         cortex_m::interrupt::free(|cs| G_TRANSFER.borrow(cs).replace(None).unwrap())
     });
 
+    let flags = transfer.flags();
     // Its important to clear fifo errors as the transfer is paused until it is cleared
-    if transfer.is_fifo_error() {
-        transfer.clear_fifo_error();
-    }
-    if transfer.is_transfer_complete() {
-        transfer.clear_transfer_complete();
+    transfer.clear_flags(DmaFlag::FifoError | DmaFlag::TransferComplete);
+    if flags.is_transfer_complete() {
         unsafe {
             static mut BUFFER: [u8; ARRAY_SIZE] = [0; ARRAY_SIZE];
             for (i, b) in BUFFER.iter_mut().enumerate() {

examples/stopwatch-with-ssd1306-and-interrupts-and-dma-i2c.rs

@@ -30,7 +30,7 @@ use crate::hal::{
     pac::{DMA1, I2C1},
     prelude::*,
     rcc::{Clocks, Rcc},
-    timer::{CounterUs, Event, Timer},
+    timer::{CounterUs, Event, Flag, Timer},
 };
 use core::cell::{Cell, RefCell};
 use core::fmt::Write;
@@ -265,7 +265,7 @@ fn main() -> ! {
 fn TIM2() {
     free(|cs| {
         if let Some(ref mut tim2) = TIMER_TIM2.borrow(cs).borrow_mut().deref_mut() {
-            tim2.clear_interrupt(Event::Update);
+            tim2.clear_flags(Flag::Update);
         }
 
         let cell = ELAPSED_MS.borrow(cs);

examples/stopwatch-with-ssd1306-and-interrupts.rs

@@ -27,7 +27,7 @@ use crate::hal::{
     interrupt, pac,
     prelude::*,
     rcc::{Clocks, Rcc},
-    timer::{CounterUs, Event, Timer},
+    timer::{CounterUs, Event, Flag, Timer},
 };
 use core::cell::{Cell, RefCell};
 use core::fmt::Write;
@@ -148,7 +148,7 @@ fn main() -> ! {
 fn TIM2() {
     free(|cs| {
         if let Some(ref mut tim2) = TIMER_TIM2.borrow(cs).borrow_mut().deref_mut() {
-            tim2.clear_interrupt(Event::Update);
+            tim2.clear_flags(Flag::Update);
         }
 
         let cell = ELAPSED_MS.borrow(cs);