slicing concat on another axis

core/src/ops/array/concat.rs

@@ -93,6 +93,9 @@ impl TypedOp for TypedConcat {
         start: usize,
         end: usize,
     ) -> TractResult<Option<TVec<OutletId>>> {
+        if output_axis != self.axis {
+            return Ok(Some(patch.wire_node(prefix, self.clone(), inputs)?));
+        }
         let facts =
             inputs.iter().map(|o| patch.outlet_fact(*o)).collect::<TractResult<TVec<_>>>()?;
         let offsets = self.offsets(&facts)?;

core/src/ops/cnn/conv/lazy_im2col.rs

@@ -1,15 +1,20 @@
 use crate::internal::*;
+use std::fmt::Debug;
 use std::ops::Range;
 use tract_linalg::frame::PackingWriter;
 use tract_linalg::mmm::{VirtualInput, VirtualInputSpec};
 
-#[derive(Clone, Debug, Hash)]
+#[derive(Clone, Hash)]
 pub struct LazyIm2colSpec {
     pub n_bytes_offsets: Vec<isize>,
     pub k_bytes_offsets: Vec<isize>,
 }
 
-
+impl Debug for LazyIm2colSpec {
+    fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
+        write!(f, "LazyIm2colSpec {{...}}")
+    }
+}
 
 impl LazyIm2colSpec {
     fn wrap_t<T: Datum + Copy>(&self, view: &TensorView) -> Box<dyn VirtualInput> {

core/src/ops/matmul/lir_unary.rs

@@ -32,7 +32,7 @@ impl ProtoFusedSpec {
     pub fn name(&self) -> String {
         use ProtoFusedSpec::*;
         match self {
-            AddMatMul(geo, _, _) => format!("matmul(k={})", geo.k),
+            AddMatMul(geo, _, _) => format!("matmul(k={}, {:?})", geo.k, geo),
             BinScalar(_, op) => format!("scalar{op:?}"),
             BinPerRow(_, op, _) => format!("row{op:?}"),
             BinPerCol(_, op, _) => format!("col{op:?}"),
@@ -260,7 +260,7 @@ impl Op for LirMatMulUnary {
 
     fn info(&self) -> TractResult<Vec<String>> {
         let mut infos = vec![format!(
-            "c_shape:{:?}, c_m_axis:{} c_n_axis:{} b_storage:{:?}",
+            "c_shape:{:?}, c_m_axis:{} c_n_axis:{} geometry:{:?}",
             self.c_fact, self.c_m_axis, self.c_n_axis, self.geometry,
         )];
         let (m, n) = self.m_n();

core/src/optim/mod.rs

@@ -153,7 +153,6 @@ impl<'o> OptimizerSession<'o> {
             }
         }
         while let Some(mut patch) = p.next(self, model)? {
-            debug!("Got a patch");
             patch.push_context(format!("{p:?}/{i}"));
             patch.model.check_consistency().context("checking patch internal consistency")?;
             model

linalg/src/frame/mmm/input_store.rs

@@ -49,6 +49,7 @@ impl fmt::Display for InputStoreSpec {
     }
 }
 
+
 #[derive(Clone, Debug)]
 pub enum InputStore {
     Packed {

linalg/src/x86_64_fma.rs

@@ -99,11 +99,13 @@ fn plug_avx512f(ops: &mut Ops) {
         _ => mmm::avx512_mmm_f32_128x1::mmm(),
     });
 
-    ops.mmm_f32 = Box::new(|_, _, n| match n {
-        Some(1) => unreachable!("should've been mmv"),
-        Some(2) => mmm::avx512_mmm_f32_80x2::mmm(),
-        Some(n) if n % 4 == 0 && n % 3 != 0 => mmm::avx512_mmm_f32_48x4::mmm(),
-        _ => mmm::avx512_mmm_f32_64x3::mmm(),
+    ops.mmm_f32 = Box::new(|m, _, n| match (m, n) {
+        (_, Some(1)) => unreachable!("should've been mmv"),
+        (_, Some(2)) => mmm::avx512_mmm_f32_80x2::mmm(),
+        (Some(m), _) if m <= 16 => mmm::avx512_mmm_f32_16x12::mmm(),
+        (_, Some(n)) if n % 4 == 0 && n % 3 != 0 && n < 32 => mmm::avx512_mmm_f32_48x4::mmm(),
+        (_, Some(n)) if n < 32 => mmm::avx512_mmm_f32_64x3::mmm(),
+        _ => mmm::avx512_mmm_f32_16x12::mmm(),
     });
     log::info!("mmm_f32, mmv_f32: x86_64/avx512f activated");
 }