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Special Purpose Register and Types #754

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merged 2 commits into from
May 12, 2024
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shaanrxx
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Proposed changes

The recent commit I made includes several updates. Firstly, there were corrections made to typing errors. I also added a new section, giving a brief overview about special-purpose registers found in CPUs. I also added an explanation of cache and discussed cache coherency. These changes are important as they allow Sfor more detail of the components of CPU architecture and how they operate. Due to their being so many registers, I felt it was important to start adding some of the functions of certain registers in as currently there is a short overview of the need for registers. Additionally, there are several reasons for the purpose of Cache and I wanted to add a few more reasons.

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@the-label-bot the-label-bot bot added kind/documentation kind/documentation size/M size/M labels May 11, 2024
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the-label-bot bot commented May 11, 2024

The Label Bot has predicted the following:

Category Value Confidence Applied Label
Kind documentation 0.796 ✔️
Size M 0.913 ✔️

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@shhossain shhossain left a comment

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No problem. Merging.

@shhossain shhossain merged commit cec613a into shhossain:main May 12, 2024
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@all-contributors add @shaanrxx for content

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@shhossain

I've put up a pull request to add @shaanrxx! 🎉

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thank you for accepting my changes!

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@shaanrxx You're welcome! Glad to have your contributions on board.

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2 participants