Update generated files

src/adc.rs

@@ -32,10 +32,7 @@ impl RegisterBlock {
     pub const fn fifo(&self) -> &FIFO {
         &self.fifo
     }
-    #[doc = "0x10 - Clock divider. If non-zero, CS_START_MANY will start conversions  
- at regular intervals rather than back-to-back.  
- The divider is reset when either of these fields are written.  
- Total period is 1 + INT + FRAC / 256"]
+    #[doc = "0x10 - Clock divider. If non-zero, CS_START_MANY will start conversions at regular intervals rather than back-to-back. The divider is reset when either of these fields are written. Total period is 1 + INT + FRAC / 256"]
     #[inline(always)]
     pub const fn div(&self) -> &DIV {
         &self.div
@@ -70,9 +67,9 @@ module"]
 pub type CS = crate::Reg<cs::CS_SPEC>;
 #[doc = "ADC Control and Status"]
 pub mod cs;
-#[doc = "RESULT (r) register accessor: Result of most recent ADC conversion  
+#[doc = "RESULT (rw) register accessor: Result of most recent ADC conversion  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`result::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::generic::Reg::read) this register and get [`result::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`result::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@result`]
 module"]
@@ -88,33 +85,27 @@ module"]
 pub type FCS = crate::Reg<fcs::FCS_SPEC>;
 #[doc = "FIFO control and status"]
 pub mod fcs;
-#[doc = "FIFO (r) register accessor: Conversion result FIFO  
+#[doc = "FIFO (rw) register accessor: Conversion result FIFO  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@fifo`]
 module"]
 pub type FIFO = crate::Reg<fifo::FIFO_SPEC>;
 #[doc = "Conversion result FIFO"]
 pub mod fifo;
-#[doc = "DIV (rw) register accessor: Clock divider. If non-zero, CS_START_MANY will start conversions  
- at regular intervals rather than back-to-back.  
- The divider is reset when either of these fields are written.  
- Total period is 1 + INT + FRAC / 256  
+#[doc = "DIV (rw) register accessor: Clock divider. If non-zero, CS_START_MANY will start conversions at regular intervals rather than back-to-back. The divider is reset when either of these fields are written. Total period is 1 + INT + FRAC / 256  
 
 You can [`read`](crate::generic::Reg::read) this register and get [`div::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@div`]
 module"]
 pub type DIV = crate::Reg<div::DIV_SPEC>;
-#[doc = "Clock divider. If non-zero, CS_START_MANY will start conversions  
- at regular intervals rather than back-to-back.  
- The divider is reset when either of these fields are written.  
- Total period is 1 + INT + FRAC / 256"]
+#[doc = "Clock divider. If non-zero, CS_START_MANY will start conversions at regular intervals rather than back-to-back. The divider is reset when either of these fields are written. Total period is 1 + INT + FRAC / 256"]
 pub mod div;
-#[doc = "INTR (r) register accessor: Raw Interrupts  
+#[doc = "INTR (rw) register accessor: Raw Interrupts  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@intr`]
 module"]
@@ -139,9 +130,9 @@ module"]
 pub type INTF = crate::Reg<intf::INTF_SPEC>;
 #[doc = "Interrupt Force"]
 pub mod intf;
-#[doc = "INTS (r) register accessor: Interrupt status after masking &amp; forcing  
+#[doc = "INTS (rw) register accessor: Interrupt status after masking &amp; forcing  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ints::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ints`]
 module"]

src/adc/cs.rs

@@ -2,26 +2,21 @@
 pub type R = crate::R<CS_SPEC>;
 #[doc = "Register `CS` writer"]
 pub type W = crate::W<CS_SPEC>;
-#[doc = "Field `EN` reader - Power on ADC and enable its clock.  
- 1 - enabled. 0 - disabled."]
+#[doc = "Field `EN` reader - Power on ADC and enable its clock. 1 - enabled. 0 - disabled."]
 pub type EN_R = crate::BitReader;
-#[doc = "Field `EN` writer - Power on ADC and enable its clock.  
- 1 - enabled. 0 - disabled."]
+#[doc = "Field `EN` writer - Power on ADC and enable its clock. 1 - enabled. 0 - disabled."]
 pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `TS_EN` reader - Power on temperature sensor. 1 - enabled. 0 - disabled."]
 pub type TS_EN_R = crate::BitReader;
 #[doc = "Field `TS_EN` writer - Power on temperature sensor. 1 - enabled. 0 - disabled."]
 pub type TS_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `START_ONCE` reader - Start a single conversion. Self-clearing. Ignored if start_many is asserted."]
-pub type START_ONCE_R = crate::BitReader;
 #[doc = "Field `START_ONCE` writer - Start a single conversion. Self-clearing. Ignored if start_many is asserted."]
 pub type START_ONCE_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `START_MANY` reader - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes."]
 pub type START_MANY_R = crate::BitReader;
 #[doc = "Field `START_MANY` writer - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes."]
 pub type START_MANY_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `READY` reader - 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed.  
- 0 whilst conversion in progress."]
+#[doc = "Field `READY` reader - 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed. 0 whilst conversion in progress."]
 pub type READY_R = crate::BitReader;
 #[doc = "Field `ERR` reader - The most recent ADC conversion encountered an error; result is undefined or noisy."]
 pub type ERR_R = crate::BitReader;
@@ -33,19 +28,12 @@ pub type ERR_STICKY_W<'a, REG> = crate::BitWriter1C<'a, REG>;
 pub type AINSEL_R = crate::FieldReader;
 #[doc = "Field `AINSEL` writer - Select analog mux input. Updated automatically in round-robin mode."]
 pub type AINSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
-#[doc = "Field `RROBIN` reader - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable.  
- Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion.  
- The first channel to be sampled will be the one currently indicated by AINSEL.  
- AINSEL will be updated after each conversion with the newly-selected channel."]
+#[doc = "Field `RROBIN` reader - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. The first channel to be sampled will be the one currently indicated by AINSEL. AINSEL will be updated after each conversion with the newly-selected channel."]
 pub type RROBIN_R = crate::FieldReader;
-#[doc = "Field `RROBIN` writer - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable.  
- Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion.  
- The first channel to be sampled will be the one currently indicated by AINSEL.  
- AINSEL will be updated after each conversion with the newly-selected channel."]
+#[doc = "Field `RROBIN` writer - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. The first channel to be sampled will be the one currently indicated by AINSEL. AINSEL will be updated after each conversion with the newly-selected channel."]
 pub type RROBIN_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
 impl R {
-    #[doc = "Bit 0 - Power on ADC and enable its clock.  
- 1 - enabled. 0 - disabled."]
+    #[doc = "Bit 0 - Power on ADC and enable its clock. 1 - enabled. 0 - disabled."]
     #[inline(always)]
     pub fn en(&self) -> EN_R {
         EN_R::new((self.bits & 1) != 0)
@@ -55,18 +43,12 @@ impl R {
     pub fn ts_en(&self) -> TS_EN_R {
         TS_EN_R::new(((self.bits >> 1) & 1) != 0)
     }
-    #[doc = "Bit 2 - Start a single conversion. Self-clearing. Ignored if start_many is asserted."]
-    #[inline(always)]
-    pub fn start_once(&self) -> START_ONCE_R {
-        START_ONCE_R::new(((self.bits >> 2) & 1) != 0)
-    }
     #[doc = "Bit 3 - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes."]
     #[inline(always)]
     pub fn start_many(&self) -> START_MANY_R {
         START_MANY_R::new(((self.bits >> 3) & 1) != 0)
     }
-    #[doc = "Bit 8 - 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed.  
- 0 whilst conversion in progress."]
+    #[doc = "Bit 8 - 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed. 0 whilst conversion in progress."]
     #[inline(always)]
     pub fn ready(&self) -> READY_R {
         READY_R::new(((self.bits >> 8) & 1) != 0)
@@ -86,18 +68,14 @@ impl R {
     pub fn ainsel(&self) -> AINSEL_R {
         AINSEL_R::new(((self.bits >> 12) & 7) as u8)
     }
-    #[doc = "Bits 16:20 - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable.  
- Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion.  
- The first channel to be sampled will be the one currently indicated by AINSEL.  
- AINSEL will be updated after each conversion with the newly-selected channel."]
+    #[doc = "Bits 16:20 - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. The first channel to be sampled will be the one currently indicated by AINSEL. AINSEL will be updated after each conversion with the newly-selected channel."]
     #[inline(always)]
     pub fn rrobin(&self) -> RROBIN_R {
         RROBIN_R::new(((self.bits >> 16) & 0x1f) as u8)
     }
 }
 impl W {
-    #[doc = "Bit 0 - Power on ADC and enable its clock.  
- 1 - enabled. 0 - disabled."]
+    #[doc = "Bit 0 - Power on ADC and enable its clock. 1 - enabled. 0 - disabled."]
     #[inline(always)]
     #[must_use]
     pub fn en(&mut self) -> EN_W<CS_SPEC> {
@@ -133,10 +111,7 @@ impl W {
     pub fn ainsel(&mut self) -> AINSEL_W<CS_SPEC> {
         AINSEL_W::new(self, 12)
     }
-    #[doc = "Bits 16:20 - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable.  
- Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion.  
- The first channel to be sampled will be the one currently indicated by AINSEL.  
- AINSEL will be updated after each conversion with the newly-selected channel."]
+    #[doc = "Bits 16:20 - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. The first channel to be sampled will be the one currently indicated by AINSEL. AINSEL will be updated after each conversion with the newly-selected channel."]
     #[inline(always)]
     #[must_use]
     pub fn rrobin(&mut self) -> RROBIN_W<CS_SPEC> {

src/adc/div.rs

@@ -36,10 +36,7 @@ impl W {
         INT_W::new(self, 8)
     }
 }
-#[doc = "Clock divider. If non-zero, CS_START_MANY will start conversions  
- at regular intervals rather than back-to-back.  
- The divider is reset when either of these fields are written.  
- Total period is 1 + INT + FRAC / 256  
+#[doc = "Clock divider. If non-zero, CS_START_MANY will start conversions at regular intervals rather than back-to-back. The divider is reset when either of these fields are written. Total period is 1 + INT + FRAC / 256  
 
 You can [`read`](crate::generic::Reg::read) this register and get [`div::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DIV_SPEC;

src/adc/fifo.rs

@@ -1,8 +1,14 @@
 #[doc = "Register `FIFO` reader"]
 pub type R = crate::R<FIFO_SPEC>;
-#[doc = "Field `VAL` reader - "]
+#[doc = "Register `FIFO` writer"]
+pub type W = crate::W<FIFO_SPEC>;
+#[doc = "Field `VAL` reader -   
+
+The field is **modified** in some way after a read operation."]
 pub type VAL_R = crate::FieldReader<u16>;
-#[doc = "Field `ERR` reader - 1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted."]
+#[doc = "Field `ERR` reader - 1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted.  
+
+The field is **modified** in some way after a read operation."]
 pub type ERR_R = crate::BitReader;
 impl R {
     #[doc = "Bits 0:11"]
@@ -16,15 +22,22 @@ impl R {
         ERR_R::new(((self.bits >> 15) & 1) != 0)
     }
 }
+impl W {}
 #[doc = "Conversion result FIFO  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FIFO_SPEC;
 impl crate::RegisterSpec for FIFO_SPEC {
     type Ux = u32;
 }
 #[doc = "`read()` method returns [`fifo::R`](R) reader structure"]
 impl crate::Readable for FIFO_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`fifo::W`](W) writer structure"]
+impl crate::Writable for FIFO_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
 #[doc = "`reset()` method sets FIFO to value 0"]
 impl crate::Resettable for FIFO_SPEC {
     const RESET_VALUE: u32 = 0;

src/adc/inte.rs

@@ -2,23 +2,19 @@
 pub type R = crate::R<INTE_SPEC>;
 #[doc = "Register `INTE` writer"]
 pub type W = crate::W<INTE_SPEC>;
-#[doc = "Field `FIFO` reader - Triggered when the sample FIFO reaches a certain level.  
- This level can be programmed via the FCS_THRESH field."]
+#[doc = "Field `FIFO` reader - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."]
 pub type FIFO_R = crate::BitReader;
-#[doc = "Field `FIFO` writer - Triggered when the sample FIFO reaches a certain level.  
- This level can be programmed via the FCS_THRESH field."]
+#[doc = "Field `FIFO` writer - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."]
 pub type FIFO_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
-    #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level.  
- This level can be programmed via the FCS_THRESH field."]
+    #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."]
     #[inline(always)]
     pub fn fifo(&self) -> FIFO_R {
         FIFO_R::new((self.bits & 1) != 0)
     }
 }
 impl W {
-    #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level.  
- This level can be programmed via the FCS_THRESH field."]
+    #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."]
     #[inline(always)]
     #[must_use]
     pub fn fifo(&mut self) -> FIFO_W<INTE_SPEC> {

src/adc/intf.rs

@@ -2,23 +2,19 @@
 pub type R = crate::R<INTF_SPEC>;
 #[doc = "Register `INTF` writer"]
 pub type W = crate::W<INTF_SPEC>;
-#[doc = "Field `FIFO` reader - Triggered when the sample FIFO reaches a certain level.  
- This level can be programmed via the FCS_THRESH field."]
+#[doc = "Field `FIFO` reader - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."]
 pub type FIFO_R = crate::BitReader;
-#[doc = "Field `FIFO` writer - Triggered when the sample FIFO reaches a certain level.  
- This level can be programmed via the FCS_THRESH field."]
+#[doc = "Field `FIFO` writer - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."]
 pub type FIFO_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
-    #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level.  
- This level can be programmed via the FCS_THRESH field."]
+    #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."]
     #[inline(always)]
     pub fn fifo(&self) -> FIFO_R {
         FIFO_R::new((self.bits & 1) != 0)
     }
 }
 impl W {
-    #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level.  
- This level can be programmed via the FCS_THRESH field."]
+    #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."]
     #[inline(always)]
     #[must_use]
     pub fn fifo(&mut self) -> FIFO_W<INTF_SPEC> {