Merge pull request #651 from ithinuel/migrate-to-edition-2021

Migrate rp2040-hal to edition 2021

rp2040-hal/Cargo.toml

@@ -2,7 +2,7 @@
 name = "rp2040-hal"
 version = "0.9.0-alpha.1"
 authors = ["The rp-rs Developers"]
-edition = "2018"
+edition = "2021"
 homepage = "https://github.com/rp-rs/rp-hal"
 description = "A Rust Embeded-HAL impl for the rp2040 microcontroller"
 license = "MIT OR Apache-2.0"

rp2040-hal/src/adc.rs

@@ -118,17 +118,15 @@
 
 use core::convert::Infallible;
 use core::marker::PhantomData;
-
-use crate::dma;
-use hal::adc::{Channel, OneShot};
-use pac::dma::ch::ch_ctrl_trig::TREQ_SEL_A;
-use pac::{ADC, RESETS};
+use embedded_hal::adc::{Channel, OneShot};
 
 use crate::{
+    dma,
     gpio::{
         bank0::{Gpio26, Gpio27, Gpio28, Gpio29},
         AnyPin, DynPinId, Function, OutputEnableOverride, Pin, PullType, ValidFunction,
     },
+    pac::{dma::ch::ch_ctrl_trig::TREQ_SEL_A, ADC, RESETS},
     resets::SubsystemReset,
 };
 

rp2040-hal/src/clocks/macros.rs

@@ -81,7 +81,7 @@ macro_rules! clock {
                     false
                 }
                 fn variant(&self) -> [<$reg:camel SrcType>] {
-                    [<$reg:camel SrcType>]::Src(pac::clocks::[<$reg _ctrl>]::SRC_A::$src_variant)
+                    [<$reg:camel SrcType>]::Src($crate::pac::clocks::[<$reg _ctrl>]::SRC_A::$src_variant)
                 }
             })*
 
@@ -100,12 +100,12 @@ macro_rules! clock {
                 }
             }
 
-            #[doc = "Holds register value for ClockSource for `"$name"`"]
+            #[doc = "Holds register value for ClockSource for `" $name "`"]
             pub enum [<$reg:camel SrcType>] {
-                #[doc = "Contains a valid clock source register value that is to be used to set a clock as glitchless source for `"$name"`"]
-                Src(pac::clocks::[<$reg _ctrl>]::SRC_A),
-                #[doc = "Contains a valid clock source register value that is to be used to set a clock as aux source for `"$name"`"]
-                Aux(pac::clocks::[<$reg _ctrl>]::AUXSRC_A)
+                #[doc = "Contains a valid clock source register value that is to be used to set a clock as glitchless source for `" $name "`"]
+                Src($crate::pac::clocks::[<$reg _ctrl>]::SRC_A),
+                #[doc = "Contains a valid clock source register value that is to be used to set a clock as aux source for `" $name "`"]
+                Aux($crate::pac::clocks::[<$reg _ctrl>]::AUXSRC_A)
             }
 
             impl [<$reg:camel SrcType>] {
@@ -116,14 +116,14 @@ macro_rules! clock {
                     }
                 }
 
-                fn unwrap_src(&self) -> pac::clocks::[<$reg _ctrl>]::SRC_A{
+                fn unwrap_src(&self) -> $crate::pac::clocks::[<$reg _ctrl>]::SRC_A{
                     match self {
                         Self::Src(v) => *v,
                         Self::Aux(_) => panic!(),
                     }
                 }
 
-                fn unwrap_aux(&self) -> pac::clocks::[<$reg _ctrl>]::AUXSRC_A {
+                fn unwrap_aux(&self) -> $crate::pac::clocks::[<$reg _ctrl>]::AUXSRC_A {
                     match self {
                         Self::Src(_) => panic!(),
                         Self::Aux(v) => *v
@@ -166,20 +166,20 @@ macro_rules! clock {
 
                     ChangingClockToken{
                         clock: PhantomData::<$name>,
-                        clock_nr: pac::clocks::clk_ref_ctrl::SRC_A::CLKSRC_CLK_REF_AUX as u8,
+                        clock_nr: $crate::pac::clocks::clk_ref_ctrl::SRC_A::CLKSRC_CLK_REF_AUX as u8,
                     }
                 }
             }
 
             impl Clock for $name {
                 type Variant = [<$reg:camel SrcType>];
 
-                #[doc = "Get operating frequency for `"$name"`"]
+                #[doc = "Get operating frequency for `" $name "`"]
                 fn freq(&self) -> HertzU32 {
                     self.frequency
                 }
 
-                #[doc = "Configure `"$name"`"]
+                #[doc = "Configure `" $name "`"]
                 fn configure_clock<S: ValidSrc<$name>>(&mut self, src: &S, freq: HertzU32) -> Result<(), ClockError>{
                     let src_freq: HertzU32 = src.get_freq().into();
 
@@ -285,14 +285,14 @@ macro_rules! divisable_clock {
 macro_rules! stoppable_clock {
     ($name:ident, $reg:ident) => {
         $crate::paste::paste!{
-            #[doc = "Holds register value for ClockSource for `"$name"`"]
+            #[doc = "Holds register value for ClockSource for `" $name "`"]
             pub enum [<$reg:camel SrcType>] {
-                #[doc = "Contains a valid clock source register value that is to be used to set a clock as aux source for `"$name"`"]
-                Aux(pac::clocks::[<$reg _ctrl>]::AUXSRC_A)
+                #[doc = "Contains a valid clock source register value that is to be used to set a clock as aux source for `" $name "`"]
+                Aux($crate::pac::clocks::[<$reg _ctrl>]::AUXSRC_A)
             }
 
             impl [<$reg:camel SrcType>] {
-                fn unwrap_aux(&self) -> pac::clocks::[<$reg _ctrl>]::AUXSRC_A {
+                fn unwrap_aux(&self) -> $crate::pac::clocks::[<$reg _ctrl>]::AUXSRC_A {
                    match self {
                        Self::Aux(v) => *v
                    }
@@ -325,12 +325,12 @@ macro_rules! stoppable_clock {
             impl Clock for $name {
                 type Variant = [<$reg:camel SrcType>];
 
-                #[doc = "Get operating frequency for `"$name"`"]
+                #[doc = "Get operating frequency for `" $name "`"]
                 fn freq(&self) -> HertzU32 {
                     self.frequency
                 }
 
-                #[doc = "Configure `"$name"`"]
+                #[doc = "Configure `" $name "`"]
                 fn configure_clock<S: ValidSrc<$name>>(&mut self, src: &S, freq: HertzU32) -> Result<(), ClockError>{
                     let src_freq: HertzU32 = src.get_freq().into();
 
@@ -398,7 +398,7 @@ macro_rules! base_clock {
                     true
                 }
                 fn variant(&self) -> [<$reg:camel SrcType>] {
-                    [<$reg:camel SrcType>]::Aux(pac::clocks::[<$reg _ctrl>]::AUXSRC_A::$variant)
+                    [<$reg:camel SrcType>]::Aux($crate::pac::clocks::[<$reg _ctrl>]::AUXSRC_A::$variant)
                 }
             })*
 

rp2040-hal/src/clocks/mod.rs

@@ -61,8 +61,11 @@
 //! ```
 //!
 //! See [Chapter 2 Section 15](https://datasheets.raspberrypi.org/rp2040/rp2040_datasheet.pdf) for more details
+use core::{convert::Infallible, marker::PhantomData};
+use fugit::{HertzU32, RateExtU32};
 
 use crate::{
+    pac::{self, CLOCKS, PLL_SYS, PLL_USB, RESETS, XOSC},
     pll::{
         common_configs::{PLL_SYS_125MHZ, PLL_USB_48MHZ},
         setup_pll_blocking, Error as PllError, Locked, PhaseLockedLoop,
@@ -71,10 +74,6 @@ use crate::{
     watchdog::Watchdog,
     xosc::{setup_xosc_blocking, CrystalOscillator, Error as XoscError, Stable},
 };
-use core::{convert::Infallible, marker::PhantomData};
-use fugit::HertzU32;
-use fugit::RateExtU32;
-use pac::{CLOCKS, PLL_SYS, PLL_USB, RESETS, XOSC};
 
 #[macro_use]
 mod macros;

rp2040-hal/src/dma/mod.rs

@@ -22,20 +22,23 @@
 //! automatic continuous ring buffers consisting of two aligned buffers being read or written
 //! alternatingly.
 
-use crate::{resets::SubsystemReset, typelevel::Sealed};
 use core::marker::PhantomData;
 use embedded_dma::{ReadBuffer, WriteBuffer};
-use rp2040_pac::DMA;
+
+use crate::{
+    pac::{self, DMA},
+    resets::SubsystemReset,
+    typelevel::Sealed,
+};
+// Export these types for easier use by external code
+pub use crate::dma::single_channel::SingleChannel;
 
 // Bring in our submodules
 pub mod bidirectional;
 pub mod double_buffer;
 pub mod single_buffer;
 mod single_channel;
 
-// Export these types for easier use by external code
-pub use crate::dma::single_channel::SingleChannel;
-
 /// DMA unit.
 pub trait DMAExt: Sealed {
     /// Splits the DMA unit into its individual channels.
@@ -134,16 +137,16 @@ channels! {
 }
 
 trait ChannelRegs {
-    unsafe fn ptr() -> *const rp2040_pac::dma::CH;
-    fn regs(&self) -> &rp2040_pac::dma::CH;
+    unsafe fn ptr() -> *const pac::dma::CH;
+    fn regs(&self) -> &pac::dma::CH;
 }
 
 impl<CH: ChannelIndex> ChannelRegs for Channel<CH> {
-    unsafe fn ptr() -> *const rp2040_pac::dma::CH {
-        &(*rp2040_pac::DMA::ptr()).ch[CH::id() as usize] as *const _
+    unsafe fn ptr() -> *const pac::dma::CH {
+        &(*pac::DMA::ptr()).ch[CH::id() as usize] as *const _
     }
 
-    fn regs(&self) -> &rp2040_pac::dma::CH {
+    fn regs(&self) -> &pac::dma::CH {
         unsafe { &*Self::ptr() }
     }
 }

rp2040-hal/src/dma/single_channel.rs

@@ -1,4 +1,4 @@
-use rp2040_pac::DMA;
+use crate::pac::DMA;
 
 use super::{Channel, ChannelIndex, Pace, ReadTarget, WriteTarget};
 use crate::{
@@ -13,7 +13,7 @@ pub trait SingleChannel: Sealed {
     /// Returns the registers associated with this DMA channel.
     ///
     /// In the case of channel pairs, this returns the first channel.
-    fn ch(&self) -> &rp2040_pac::dma::CH;
+    fn ch(&self) -> &crate::pac::dma::CH;
     /// Returns the index of the DMA channel.
     fn id(&self) -> u8;
 
@@ -113,13 +113,13 @@ pub trait SingleChannel: Sealed {
 pub trait ChannelPair: SingleChannel + Sealed {
     /// Returns the registers associated with the second DMA channel associated with this channel
     /// pair.
-    fn ch2(&self) -> &rp2040_pac::dma::CH;
+    fn ch2(&self) -> &crate::pac::dma::CH;
     /// Returns the index of the second DMA channel.
     fn id2(&self) -> u8;
 }
 
 impl<CH: ChannelIndex> SingleChannel for Channel<CH> {
-    fn ch(&self) -> &rp2040_pac::dma::CH {
+    fn ch(&self) -> &crate::pac::dma::CH {
         self.regs()
     }
 
@@ -131,7 +131,7 @@ impl<CH: ChannelIndex> SingleChannel for Channel<CH> {
 impl<CH: ChannelIndex> Sealed for Channel<CH> {}
 
 impl<CH1: ChannelIndex, CH2: ChannelIndex> SingleChannel for (Channel<CH1>, Channel<CH2>) {
-    fn ch(&self) -> &rp2040_pac::dma::CH {
+    fn ch(&self) -> &crate::pac::dma::CH {
         self.0.regs()
     }
 
@@ -245,7 +245,7 @@ impl<CH: SingleChannel> ChannelConfig for CH {
     fn start(&mut self) {
         // Safety: The write does not interfere with any other writes, it only affects this
         // channel.
-        unsafe { &*rp2040_pac::DMA::ptr() }
+        unsafe { &*crate::pac::DMA::ptr() }
             .multi_chan_trigger
             .write(|w| unsafe { w.bits(1 << self.id()) });
     }
@@ -254,7 +254,7 @@ impl<CH: SingleChannel> ChannelConfig for CH {
         // Safety: The write does not interfere with any other writes, it only affects this
         // channel and other (which we have an exclusive borrow of).
         let channel_flags = 1 << self.id() | 1 << other.id();
-        unsafe { &*rp2040_pac::DMA::ptr() }
+        unsafe { &*crate::pac::DMA::ptr() }
             .multi_chan_trigger
             .write(|w| unsafe { w.bits(channel_flags) });
     }

rp2040-hal/src/float/div.rs

@@ -1,5 +1,5 @@
 use super::Float;
-use crate::rom_data;
+use crate::{pac, rom_data};
 
 // Make sure this stays as a separate call, because when it's inlined the
 // compiler will move the save of the registers used to contain the divider

rp2040-hal/src/gpio/mod.rs

@@ -43,6 +43,7 @@ pub use embedded_hal::digital::v2::PinState;
 
 use crate::{
     atomic_register_access::{write_bitmask_clear, write_bitmask_set},
+    pac,
     sio::Sio,
     typelevel::{self, Sealed},
 };
@@ -169,8 +170,8 @@ pub struct Pin<I: PinId, F: func::Function, P: PullType> {
 /// The uniqueness of the pin is not verified. User must make sure no other instance of that specific
 /// pin exists at the same time.
 pub unsafe fn new_pin(id: DynPinId) -> Pin<DynPinId, DynFunction, DynPullType> {
+    use pac::io_bank0::gpio::gpio_ctrl::FUNCSEL_A;
     use pin::pin_sealed::PinIdOps;
-    use rp2040_pac::io_bank0::gpio::gpio_ctrl::FUNCSEL_A;
 
     let funcsel = id
         .io_ctrl()
@@ -941,8 +942,8 @@ macro_rules! gpio {
         paste::paste!{
             #[doc = "Pin bank " [<$bank>] ]
             pub mod [<$bank:snake>] {
+                use $crate::pac::{[<IO_ $bank:upper>],[<PADS_ $bank:upper>]};
                 use crate::sio::[<SioGpio $bank>];
-                use pac::{[<IO_ $bank:upper>],[<PADS_ $bank:upper>]};
                 use super::{Pin, pin, pull, func};
                 $(pub use super::pin::[<$bank:lower>]::[<$prefix $id>];)*
 
@@ -956,15 +957,15 @@ macro_rules! gpio {
 
                 impl Pins {
                     /// Take ownership of the PAC peripherals and SIO slice and split it into discrete [`Pin`]s
-                    pub fn new(io : [<IO_ $bank:upper>], pads: [<PADS_ $bank:upper>], sio: [<SioGpio $bank>], reset : &mut pac::RESETS) -> Self {
+                    pub fn new(io : [<IO_ $bank:upper>], pads: [<PADS_ $bank:upper>], sio: [<SioGpio $bank>], reset : &mut $crate::pac::RESETS) -> Self {
                         use crate::resets::SubsystemReset;
                         pads.reset_bring_down(reset);
                         io.reset_bring_down(reset);
 
                         {
                             use $crate::gpio::pin::DynBankId;
                             // SAFETY: this function owns the whole bank that will be affected.
-                            let sio = unsafe { &*pac::SIO::PTR };
+                            let sio = unsafe { &*$crate::pac::SIO::PTR };
                             if DynBankId::$bank == DynBankId::Bank0 {
                                 sio.gpio_oe.reset();
                                 sio.gpio_out.reset();

rp2040-hal/src/gpio/pin.rs

@@ -26,6 +26,8 @@
 //! This modules bridges that gap by adding a trait definition per register type and implementing it
 //! for each of the relevant registers.
 
+use crate::typelevel::Sealed;
+
 use super::{DynFunction, DynPullType};
 
 pub(crate) mod pin_sealed;
@@ -41,16 +43,16 @@ pub enum DynBankId {
 }
 
 /// Type-level `enum` for the pin's bank ID.
-pub trait BankId: crate::typelevel::Sealed {}
+pub trait BankId: Sealed {}
 
 /// Type-level `variant` of `BankId`
 pub struct BankBank0;
-impl crate::typelevel::Sealed for BankBank0 {}
+impl Sealed for BankBank0 {}
 impl BankId for BankBank0 {}
 
 /// Type-level `variant` of `BankId`
 pub struct BankQspi;
-impl crate::typelevel::Sealed for BankQspi {}
+impl Sealed for BankQspi {}
 impl BankId for BankQspi {}
 
 /// Type-level `enum` for the pin Id (pin number + bank).
@@ -125,7 +127,7 @@ pub mod qspi {
 }
 
 pub(crate) fn set_function<P: PinId>(pin: &P, function: DynFunction) {
-    use pac::io_bank0::gpio::gpio_ctrl::FUNCSEL_A;
+    use crate::pac::io_bank0::gpio::gpio_ctrl::FUNCSEL_A;
     let funcsel = match function {
         DynFunction::Xip => FUNCSEL_A::JTAG,
         DynFunction::Spi => FUNCSEL_A::SPI,