Don't mention NVIC in the examples.

Because in RISC-V mode the interrupt controller is the Xh3irq. Unless its the vector-table example, which only works on Arm currently.

rp235x-hal-examples/src/bin/gpio_irq_example.rs

@@ -125,12 +125,16 @@ fn main() -> ! {
         GLOBAL_PINS.borrow(cs).replace(Some((led, in_pin)));
     });
 
-    // Unmask the IO_BANK0 IRQ so that the NVIC interrupt controller
-    // will jump to the interrupt function when the interrupt occurs.
-    // We do this last so that the interrupt can't go off while
-    // it is in the middle of being configured
+    // Unmask the IRQ for I/O Bank 0 so that the RP2350's interrupt controller
+    // (NVIC in Arm mode, or Xh3irq in RISC-V mode) will jump to the interrupt
+    // function when the interrupt occurs. We do this last so that the interrupt
+    // can't go off while it is in the middle of being configured
     unsafe {
         hal::arch::interrupt_unmask(hal::pac::Interrupt::IO_IRQ_BANK0);
+    }
+
+    // Enable interrupts on this core
+    unsafe {
         hal::arch::interrupt_enable();
     }
 

rp235x-hal-examples/src/bin/i2c_async.rs

@@ -94,14 +94,16 @@ async fn demo() {
         clocks.system_clock.freq(),
     );
 
-    // Unmask the interrupt in the NVIC to let the core wake up & enter the interrupt handler.
-    // Each core has its own NVIC so these needs to executed from the core where the IRQ are
-    // expected.
+    // Unmask the IRQ for I2C0. We do this after the driver init so that the
+    // interrupt can't go off while it is in the middle of being configured
     unsafe {
         hal::arch::interrupt_unmask(hal::pac::Interrupt::I2C0_IRQ);
-        hal::arch::interrupt_enable();
     }
 
+    // Enable interrupts on this core
+    unsafe {
+        hal::arch::interrupt_enable();
+    }
     // Asynchronously write three bytes to the I²C device with 7-bit address 0x2C
     i2c.write(0x76u8, &[1, 2, 3]).await.unwrap();
 

rp235x-hal-examples/src/bin/i2c_async_cancelled.rs

@@ -96,9 +96,14 @@ async fn demo() {
         clocks.system_clock.freq(),
     );
 
-    // Unmask the interrupt in the NVIC to let the core wake up & enter the interrupt handler.
+    // Unmask the IRQ for I2C0. We do this after the driver init so that the
+    // interrupt can't go off while it is in the middle of being configured
     unsafe {
         hal::arch::interrupt_unmask(hal::pac::Interrupt::I2C0_IRQ);
+    }
+
+    // Enable interrupts on this core
+    unsafe {
         hal::arch::interrupt_enable();
     }
 

rp235x-hal-examples/src/bin/powman_test.rs

@@ -124,8 +124,15 @@ fn main() -> ! {
     print_aot_status(&mut powman);
     _ = writeln!(&GLOBAL_UART, "AOT time: 0x{:016x}", powman.aot_get_time());
 
+    // Unmask the IRQ for POWMAN's Timer. We do this after the driver init so
+    // that the interrupt can't go off while it is in the middle of being
+    // configured
+    unsafe {
+        hal::arch::interrupt_unmask(hal::pac::Interrupt::POWMAN_IRQ_TIMER);
+    }
+
+    // Enable interrupts on this core
     unsafe {
-        hal::arch::interrupt_unmask(pac::Interrupt::POWMAN_IRQ_TIMER);
         hal::arch::interrupt_enable();
     }
 

rp235x-hal-examples/src/bin/pwm_irq_input.rs

@@ -140,11 +140,16 @@ fn main() -> ! {
         GLOBAL_PINS.borrow(cs).replace(Some((led, input_pin, pwm)));
     });
 
-    // Unmask the IO_BANK0 IRQ so that the interrupt controller will jump to the
-    // interrupt function when the interrupt occurs. We do this last so that the
-    // interrupt can't go off while it is in the middle of being configured
+    // Unmask the IRQ for I/O Bank 0 so that the RP2350's interrupt controller
+    // (NVIC in Arm mode, or Xh3irq in RISC-V mode) will jump to the interrupt
+    // function when the interrupt occurs. We do this last so that the interrupt
+    // can't go off while it is in the middle of being configured
     unsafe {
         hal::arch::interrupt_unmask(hal::pac::Interrupt::IO_IRQ_BANK0);
+    }
+
+    // Enable interrupts on this core
+    unsafe {
         hal::arch::interrupt_enable();
     }