Add an initial non-optimized ARM NEON kernel #30
Merged
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This is just a copy of the base kernel that has been tweaked to take advantage of the extra available SIMD registers (32 instead of 16 as in SSE), use FMA instructions and unroll the inner loop.
On an AWS c6g.xlarge instance (Graviton 2, 4 vCPU) this achieves ~114 GFLOPS vs ~65 with the base kernel. For comparison OpenBLAS achieves ~150 GFLOPS.
Related issues: #18, #27