ACT test draft for Smcdeleg/Ssccfg

[adlr]

Description

Provide a detailed description of the changes performed by the PR.

Draft PR for Smcdeleg/Ssccfg support. Tests various ways to attempt to access instret.

Note that currently I'm not sure how to set a trap handler to handle and note illegal instruction cases. I'm open to suggestion on that.

Related Issues

Please list all the issues related to this PR. Use NA if no issues exist

Ratified/Unratified Extensions

• Ratified
• Unratified

List Extensions

List the extensions that your PR affects. In case of unratified extensions, please provide a link to the spec draft that was referred to make this PR.

Smcdeleg/Ssccfg

Reference Model Used

• SAIL - Smcsrindpr riscv/sail-riscv#369
• Spike
• Other - < SPECIFY HERE >

Mandatory Checklist:

• All tests are compliant with the test-format spec present in this repo ?
• Ran the new tests on RISCOF with SAIL/Spike as reference model successfully ?
• Ran the new tests on RISCOF in coverage mode
• Link to Google-Drive folder containing the new coverage reports (See this for more info): < SPECIFY HERE >
• Link to PR in RISCV-ISAC from which the reports were generated : < SPECIFY HERE >
• Changelog entry created with a minor patch

Optional Checklist:

• RISCV-V CTG PR link if tests were generated using it : < SPECIFY HERE >
• Were the tests hand-written/modified ?
• Have you run these on any hard DUT model ? Please specify name and provide link if possible in the description
• If you have modified arch_test.h Please provide a detailed description of the changes in the Description section above.

[allenjbaum]

"Note that currently I'm not sure how to set a trap handler to handle and note illegal instruction cases." I think what you're looking for is already implemented Tests must define the empty macro "rvtest_mtrap_routine" for any tests that might trap into mmode, and must define the empty macro "rvtest_strap_routine" for any tests that might trap into smode or hsmode, and must define the empty macro "rvtest_vtrap_routine" for any tests that might trap into vsmode. These labels will cause trap handlers at those privilege levels to be instantiated. The handles already record all state changes updated by a trap (epc, cause, vector#, etc) into the signature between a labels tsig_begin_canary: and tsig_end_canary So you shouldn't have to do anything beyond that unless you require a special handlers beyond the state saving

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On Thu, Dec 7, 2023 at 4:02 PM Andrew de los Reyes ***@***.***> wrote: Description Provide a detailed description of the changes performed by the PR. Draft PR for Smcdeleg/Ssccfg support. Tests various ways to attempt to access instret. Note that currently I'm not sure how to set a trap handler to handle and note illegal instruction cases. I'm open to suggestion on that. Related Issues Please list all the issues related to this PR. Use NA if no issues exist Ratified/Unratified Extensions - Ratified - Unratified List Extensions List the extensions that your PR affects. In case of unratified extensions, please provide a link to the spec draft that was referred to make this PR. Smcdeleg/Ssccfg Reference Model Used - SAIL - riscv/sail-riscv#369 <riscv/sail-riscv#369> - Spike - Other - < SPECIFY HERE > Mandatory Checklist: - All tests are compliant with the test-format spec present in this repo ? - Ran the new tests on RISCOF with SAIL/Spike as reference model successfully ? - Ran the new tests on RISCOF in coverage mode <https://riscof.readthedocs.io/en/stable/commands.html#coverage> - Link to Google-Drive folder containing the new coverage reports (See this <https://github.com/riscv-non-isa/riscv-arch-test/blob/main/CONTRIBUTION.md#uploading-test-stats> for more info): < SPECIFY HERE > - Link to PR in RISCV-ISAC from which the reports were generated : < SPECIFY HERE > - Changelog entry created with a minor patch Optional Checklist: - RISCV-V CTG PR link if tests were generated using it : < SPECIFY HERE > - Were the tests hand-written/modified ? - Have you run these on any hard DUT model ? Please specify name and provide link if possible in the description - If you have modified arch_test.h Please provide a detailed description of the changes in the Description section above. ------------------------------ You can view, comment on, or merge this pull request online at: #415 Commit Summary - eede9b5 <eede9b5> minstretcfg: add test for this CSR - f389646 <f389646> instret-indirect.S: Add test case for siselect/sireg File Changes (2 files <https://github.com/riscv-non-isa/riscv-arch-test/pull/415/files> ) - *A* riscv-test-suite/rv32i_m/Smcntrpmf/src/instret-indirect.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/415/files#diff-a4caa44e10669e430448c1bd8c11cac15f40f39d8f93b047865b7b4193177153> (106) - *A* riscv-test-suite/rv32i_m/Smcntrpmf/src/minstretcfg.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/415/files#diff-15064d592ca1012109a4adc89e3af8e86ae448ef36b7562e91aaacd4dbca476c> (120) Patch Links: - https://github.com/riscv-non-isa/riscv-arch-test/pull/415.patch - https://github.com/riscv-non-isa/riscv-arch-test/pull/415.diff — Reply to this email directly, view it on GitHub <#415>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AHPXVJUJLWR3I4LVE3GG3X3YIJKIRAVCNFSM6AAAAABAL3YSBGVHI2DSMVQWIX3LMV43ASLTON2WKOZSGAZTCNZQGYZTCOI> . You are receiving this because you are subscribed to this thread.Message ID: ***@***.***>

[bcstrongx]

nit, but ICOUNT is the name of an Sdtrig register. Probably best to call this READ_INSTRET?

[bcstrongx]

The comment above is wrong, should be "inhibit S-mode". Same for comments below.