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add Cortex-A72 Spectre v4 (CVE-2018-3639) mitigation #115

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add Cortex-A72 Spectre v4 (CVE-2018-3639) mitigation #115

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lilyanatia
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mitigate Spectre v4:

For Cortex-A57 and Cortex-A72:

  • Set bit 55 (disable load pass store) of CPUACTLR_EL1 (S3_1_C15_C2_0).

@lilyanatia lilyanatia mentioned this pull request Aug 11, 2020
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@fincs fincs mentioned this pull request Sep 24, 2020
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pelwell pushed a commit that referenced this pull request Oct 8, 2020
@fincs @pelwell
armstub7: Major refactoring and size improvements, see details:
14985bb 
- The bootstub has been completely rewritten taking advantage of the
  Thumb-2 instruction set, which results in major space gains
- Res0 bits of NSACR are no longer set (supersedes #85)
- CNTVOFF is set to zero, now consistent with armstub8 (supersedes #113)
- SMC instructions are now disabled, now consistent with armstub8
- ACTLR is now configured to allow Non-secure access to several CPU
  configuration registers (CPUACTLR/CPUECTLR/L2CTLR/L2ECTLR/L2ACTLR),
  which makes it possible to e.g. enable Spectre v4 mitigations directly
  in the kernel without needing a separate bootstub variant
  (potentially supersedes #115)

Free space in each affected bootstub after this commit:

  armstub7.bin:        108 bytes
  armstub8-32.bin:     104 bytes
  armstub8-32-gic.bin:  44 bytes (!)
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