dts: align PCI BAR allocation on bcm2711 and bcm2712 to start at 2GB

Fold the Pi 5 mmio-hi compatibility option into the base DTB, and shuffle the single MMIO window on bcm2711 to match. Certain devices cannot handle low addresses, e.g. by failing to enumerate or failing to route the traffic appropriately. Link: #6134 Link: #6278 Signed-off-by: Jonathan Bell <[email protected]>
raspberrypi · Sep 30, 2024 · 3d6fae8 · 3d6fae8
1 parent 7fb4db2
commit 3d6fae8
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Showing 4 changed files with 9 additions and 29 deletions.
diff --git a/arch/arm/boot/dts/broadcom/bcm2711-rpi-ds.dtsi b/arch/arm/boot/dts/broadcom/bcm2711-rpi-ds.dtsi
@@ -118,7 +118,7 @@
 
 	ranges = <0x0 0x7c000000  0x0 0xfc000000  0x0 0x03800000>,
 		 <0x0 0x40000000  0x0 0xff800000  0x0 0x00800000>,
-		 <0x6 0x00000000  0x6 0x00000000  0x0 0x40000000>,
+		 <0x6 0x00000000  0x6 0x00000000  0x0 0x80000000>,
 		 <0x0 0x00000000  0x0 0x00000000  0x0 0xfc000000>;
 	dma-ranges = <0x4 0x7c000000  0x0 0xfc000000  0x0 0x03800000>,
 		     <0x0 0x00000000  0x0 0x00000000  0x4 0x00000000>;
@@ -162,8 +162,8 @@
 
 &pcie0 {
 	reg = <0x0 0x7d500000  0x0 0x9310>;
-	ranges = <0x02000000 0x0 0xc0000000 0x6 0x00000000
-		  0x0 0x40000000>;
+	ranges = <0x02000000 0x0 0x80000000 0x6 0x00000000
+		  0x0 0x80000000>;
 };
 
 &genet {

diff --git a/arch/arm/boot/dts/overlays/README b/arch/arm/boot/dts/overlays/README
@@ -3649,8 +3649,6 @@ Params: l1ss                    Enable ASPM L1 sub-state support
                                 the MSI-MIP peripheral. Use if a) more than 8
                                 interrupt vectors are required or b) the EP
                                 requires DMA and MSI addresses to be 32bit.
-        mmio-hi                 Move the start of outbound 32bit addresses to
-                                2GB and expand 64bit outbound space to 14GB.
 
 
 [ The pcf2127-rtc overlay has been deleted. See i2c-rtc. ]

diff --git a/arch/arm/boot/dts/overlays/pciex1-compat-pi5-overlay.dts b/arch/arm/boot/dts/overlays/pciex1-compat-pi5-overlay.dts
@@ -32,29 +32,9 @@
 		};
 	};
 
-	/*
-	 * Shift the start of the 32bit outbound window to 2GB,
-	 * so there are no BARs starting at 0x0. Expand the 64bit
-	 * outbound window to use the spare 2GB.
-	 */
-	fragment@3 {
-		target = <&pciex1>;
-		__dormant__ {
-			#address-cells = <3>;
-			#size-cells = <2>;
-			ranges = <0x02000000 0x00 0x80000000
-				  0x1b 0x80000000
-				  0x00 0x7ffffffc>,
-				 <0x43000000 0x04 0x00000000
-				  0x18 0x00000000
-				  0x03 0x80000000>;
-		};
-	};
-
 	__overrides__ {
 		l1ss = <0>, "+0";
 		no-l0s = <0>, "+1";
 		no-mip = <0>, "+2";
-		mmio-hi = <0>, "+3";
 	};
 };
diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
@@ -1052,12 +1052,14 @@
 			msi-controller;
 			msi-parent = <&mip1>;
 
-			ranges = <0x02000000 0x00 0x00000000
-				  0x1b 0x00000000
-				  0x00 0xfffffffc>,
+			// 2GB, 32-bit, non-prefetchable at PCIe 00_80000000
+			ranges = <0x02000000 0x00 0x80000000
+				  0x1b 0x80000000
+				  0x00 0x80000000>,
+			// 14GB, 64-bit, prefetchable at PCIe 04_00000000
 				 <0x43000000 0x04 0x00000000
 				  0x18 0x00000000
-				  0x03 0x00000000>;
+				  0x03 0x80000000>;
 
 			dma-ranges = <0x03000000 0x10 0x00000000
 				      0x00 0x00000000