sw/hello_world: Verify UART output

target/sim/sw/host/apps/hello_world/src/hello_world.c

@@ -4,12 +4,15 @@
 
 #include "host.c"
 
-// Assumes bypass FLL mode and SIM_WITHOUT_HBM
+// Frequency at which the UART peripheral is clocked
 #define PERIPH_FREQ 1000000000
 
 int main() {
     init_uart(PERIPH_FREQ, 115200);
     asm volatile("fence" : : : "memory");
     print_uart("Hello world!\r\n");
+    // Artificial delay to ensure last symbol has been transmitted
+    // (just waiting for the UART TSR register to be empty is not sufficient)
+    for (int i = 0; i < 5000; i++) asm volatile ("nop" : : : "memory");
     return 0;
 }

target/sim/sw/host/apps/hello_world/verify.py

@@ -0,0 +1,55 @@
+#!/usr/bin/env python3
+# Copyright 2023 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Luca Colagrande <[email protected]>
+
+import argparse
+from pathlib import Path
+import sys
+
+sys.path.append(str(Path(__file__).parent / '../../../../../../deps/snitch_cluster/util/sim/'))
+from simulate import run_simulation  # noqa: E402
+
+UART_LOG = str(Path(__file__).parent / '../../../../uart0.log')
+EXPECTED_OUTPUT = "Hello world!\r\n"
+
+
+def parse_args():
+    # Argument parsing
+    parser = argparse.ArgumentParser(allow_abbrev=True)
+    parser.add_argument(
+        'simulator',
+        help='The simulator to be used',
+    )
+    parser.add_argument(
+        'sim_bin',
+        help='The simulator binary to be used to start the simulation',
+    )
+    parser.add_argument(
+        'snitch_bin',
+        help='The Snitch binary to be executed by the simulated Snitch hardware')
+    return parser.parse_args()
+
+
+def main():
+    args = parse_args()
+    cmd = f"{args.sim_bin} {args.snitch_bin}"
+    result = run_simulation(cmd, args.simulator, {})
+    actual_output = ''
+    with open(UART_LOG, 'rb') as file:
+        actual_output = file.read().decode('ascii')
+    if result == 0:
+        if actual_output == EXPECTED_OUTPUT:
+            print(f"[{Path(__file__).name}] UART output matches expected output \"{ascii(EXPECTED_OUTPUT)}\"")
+            return 0
+        else:
+            print(f"[{Path(__file__).name}] UART output \"{ascii(actual_output)}\" does not match expected output \"{ascii(EXPECTED_OUTPUT)}\"")
+            return 1
+    else:
+        return result
+
+
+if __name__ == '__main__':
+    sys.exit(main())

target/sim/sw/run-single-cluster.yaml

@@ -10,3 +10,4 @@ runs:
     cmd: ../../deps/snitch_cluster/sw/blas/gemm/verify.py {sim_bin} {elf}
           --symbols-bin ./sw/device/apps/blas/gemm/build/gemm.elf
   - elf: host/apps/hello_world/build/hello_world.elf
+    cmd: sw/host/apps/hello_world/verify.py {simulator} {sim_bin} {elf}

target/sim/test/.gitignore

@@ -0,0 +1 @@
+testharness.sv