update.sh: fix rocket-chip and L2-cache versions

Given the upstream chipsallliance/rocket-chip decision to remove support for independent builds (i.e., `make verilog`, see github.com/chipsalliance/rocket-chip/issues/3483#issuecomment-1724857339), check out the last commit before the breaking merge (#4f197707e). Similarly, check out the version of the L2 cache current at around the same time (#51d400b) to avoid further upstream drift. NOTE: Unless upstream reconsiders, this is likely the *LAST* version of the Rocket Chip to be supported for inclusion in LiteX! Signed-off-by: Gabriel Somlo <[email protected]>
litex-hub · Sep 20, 2023 · 85e155f · 85e155f
1 parent 018e941
commit 85e155f
Showing 1 changed file with 7 additions and 1 deletion.
diff --git a/pythondata_cpu_rocket/verilog/update.sh b/pythondata_cpu_rocket/verilog/update.sh
@@ -35,9 +35,15 @@ PATH=/usr/bin:${HOME}/RISCV/bin
 # grab a copy of upstream:
 rm -rf rocket-chip
 git clone --recursive https://github.com/chipsalliance/rocket-chip
+pushd rocket-chip
+# reset to last commit before dev merge that removed SBT, standalone build:
+git reset --hard 4f197707eb07d833131395a839974c186069930b
 # also grab a copy of the L2 cache repo:
-pushd rocket-chip/src/main/scala
+cd src/main/scala
 git clone https://github.com/chipsalliance/rocket-chip-inclusive-cache
+cd rocket-chip-inclusive-cache
+# also fix the L2 cache to a known, tested version:
+git reset --hard 51d400bd32131e8914c6713bfb71bef690f2fe70
 popd
 
 # make Rocket's internal bootrom jump to 0x1000_0000, as expected by LiteX: