Fix synthesis

kuznia-rdzeni · Sep 30, 2024 · f532342 · f532342
1 parent f4c15bd
commit f532342
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Showing 2 changed files with 3 additions and 2 deletions.
diff --git a/amaranth-stubs b/amaranth-stubs
diff --git a/scripts/synthesize.py b/scripts/synthesize.py
@@ -6,6 +6,7 @@
 import argparse
 
 from amaranth.build import Platform
+from amaranth.build.res import PortGroup
 from amaranth import *
 from amaranth.lib.wiring import Component, Flow, Out, connect, flipped
 
@@ -61,7 +62,7 @@ def elaborate(self, platform: Platform):
         m = Module()
 
         pins = platform.request(self.name, self.number)
-        assert isinstance(pins, Record)
+        assert isinstance(pins, PortGroup)
 
         for hier_name, member, v in self.interface.signature.flatten(self.interface):
             name = "__".join(str(x) for x in hier_name)