Fix signal assignments

kuznia-rdzeni · Aug 1, 2024 · 9f13cb1 · 9f13cb1
1 parent 5c48ed0
commit 9f13cb1
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Showing 6 changed files with 8 additions and 11 deletions.
diff --git a/coreblocks/frontend/decoder/rvc.py b/coreblocks/frontend/decoder/rvc.py
@@ -291,7 +291,7 @@ def elaborate(self, platform):
 
         res = self.instr_mux(quadrant, quadrants)
 
-        # In case of illegal instruction, ouput `instr_in` to be able to save it into `mtval` CSR.
+        # In case of illegal instruction, output `instr_in` to be able to save it into `mtval` CSR.
         # Decoder would still recognize it as illegal because of quadrant != 0b11
         m.d.comb += self.instr_out.eq(Mux(res[1], res[0], self.instr_in))
 

diff --git a/coreblocks/func_blocks/fu/exception.py b/coreblocks/func_blocks/fu/exception.py
@@ -92,7 +92,7 @@ def _(arg):
                     m.d.av_comb += cause.eq(ExceptionCause.INSTRUCTION_PAGE_FAULT)
                     m.d.av_comb += mtval.eq(arg.pc + (arg.imm[1] << 1))
 
-            self.report(m, rob_id=arg.rob_id, cause=cause, pc=arg.pc)
+            self.report(m, rob_id=arg.rob_id, cause=cause, pc=arg.pc, mtval=mtval)
 
             fifo.write(m, result=0, exception=1, rob_id=arg.rob_id, rp_dst=arg.rp_dst)
 

diff --git a/coreblocks/func_blocks/fu/lsu/dummyLsu.py b/coreblocks/func_blocks/fu/lsu/dummyLsu.py
@@ -4,7 +4,6 @@
 from transactron import Method, def_method, Transaction, TModule
 from transactron.lib.connectors import FIFO, Forwarder
 from transactron.utils import DependencyContext
-from transactron.utils.transactron_helpers import extend_layout
 from transactron.lib.simultaneous import condition
 from transactron.lib.logging import HardwareLogger
 
@@ -65,9 +64,7 @@ def elaborate(self, platform):
         m.submodules.requester = requester = LSURequester(self.gen_params, self.bus)
 
         m.submodules.requests = requests = Forwarder(self.fu_layouts.issue)
-        m.submodules.results_noop = results_noop = FIFO(
-            extend_layout(self.lsu_layouts.accept, ("addr", self.gen_params.isa.xlen)), 2
-        )
+        m.submodules.results_noop = results_noop = FIFO(self.lsu_layouts.accept, 2)
         m.submodules.issued = issued = FIFO(self.fu_layouts.issue, 2)
         m.submodules.issued_noop = issued_noop = FIFO(self.fu_layouts.issue, 2)
 
@@ -109,7 +106,7 @@ def _(arg):
 
             with m.If(res["exception"]):
                 issued_noop.write(m, arg)
-                results_noop.write(m, data=0, exception=res["exception"], cause=res["cause"], addr=res["addr"])
+                results_noop.write(m, data=0, exception=res["exception"], cause=res["cause"], addr=addr)
             with m.Else():
                 issued.write(m, arg)
 
@@ -132,7 +129,7 @@ def _():
                     m.d.comb += arg.eq(issued_noop.read(m))
 
             with m.If(res["exception"]):
-                self.report(m, rob_id=arg["rob_id"], cause=res["cause"], pc=arg["pc"], mtval=arg["addr"])
+                self.report(m, rob_id=arg["rob_id"], cause=res["cause"], pc=arg["pc"], mtval=res["addr"])
 
             self.log.debug(m, 1, "accept rob_id={} result=0x{:08x} exception={}", arg.rob_id, res.data, res.exception)
 

diff --git a/coreblocks/func_blocks/fu/lsu/lsu_requester.py b/coreblocks/func_blocks/fu/lsu/lsu_requester.py
@@ -143,7 +143,7 @@ def _(addr: Value, data: Value, funct3: Value, store: Value):
                     Mux(store, ExceptionCause.STORE_ADDRESS_MISALIGNED, ExceptionCause.LOAD_ADDRESS_MISALIGNED)
                 )
 
-            return {"exception": exception, "cause": cause, "addr": addr}
+            return {"exception": exception, "cause": cause}
 
         @def_method(m, self.accept)
         def _():

diff --git a/coreblocks/interface/layouts.py b/coreblocks/interface/layouts.py
@@ -581,7 +581,7 @@ def __init__(self, gen_params: GenParams):
 
         self.issue_out = make_layout(fields.exception, fields.cause)
 
-        self.accept = make_layout(fields.data, fields.exception, fields.cause)
+        self.accept = make_layout(fields.data, fields.exception, fields.cause, fields.addr)
 
 
 class CSRRegisterLayouts:

diff --git a/coreblocks/priv/traps/exception.py b/coreblocks/priv/traps/exception.py
@@ -111,7 +111,7 @@ def _(cause, rob_id, pc, mtval):
 
         @def_method(m, self.get)
         def _():
-            return {"rob_id": self.rob_id, "cause": self.cause, "pc": self.pc, "valid": self.valid}
+            return {"rob_id": self.rob_id, "cause": self.cause, "pc": self.pc, "mtval": self.mtval, "valid": self.valid}
 
         @def_method(m, self.clear)
         def _():