Typing fixes

coreblocks/cache/icache.py

@@ -3,7 +3,7 @@
 
 from amaranth import *
 from amaranth.lib.data import View
-from amaranth.lib.memory import Memory
+import amaranth.lib.memory as memory
 from amaranth.utils import exact_log2
 
 from transactron.core import def_method, Priority, TModule
@@ -330,7 +330,7 @@ def elaborate(self, platform):
         for i in range(self.params.num_of_ways):
             way_wr = self.way_wr_en[i]
 
-            tag_mem = Memory(shape=self.tag_data_layout, depth=self.params.num_of_sets, init=[])
+            tag_mem = memory.Memory(shape=self.tag_data_layout, depth=self.params.num_of_sets, init=[])
             tag_mem_wp = tag_mem.write_port()
             tag_mem_rp = tag_mem.read_port(transparent_for=[tag_mem_wp])
             m.submodules[f"tag_mem_{i}"] = tag_mem
@@ -343,7 +343,7 @@ def elaborate(self, platform):
                 tag_mem_wp.en.eq(self.tag_wr_en & way_wr),
             ]
 
-            data_mem = Memory(
+            data_mem = memory.Memory(
                 shape=self.fetch_block_bits, depth=self.params.num_of_sets * self.params.fetch_blocks_in_line, init=[]
             )
             data_mem_wp = data_mem.write_port()

coreblocks/core_structs/rob.py

@@ -1,6 +1,6 @@
 from amaranth import *
 from amaranth.lib.data import View
-from amaranth.lib.memory import Memory
+import amaranth.lib.memory as memory
 from transactron import Method, Transaction, def_method, TModule
 from transactron.lib.metrics import *
 from coreblocks.interface.layouts import ROBLayouts
@@ -19,7 +19,7 @@ def __init__(self, gen_params: GenParams) -> None:
         self.retire = Method()
         self.done = Array(Signal() for _ in range(2**self.params.rob_entries_bits))
         self.exception = Array(Signal() for _ in range(2**self.params.rob_entries_bits))
-        self.data = Memory(shape=layouts.data_layout.size, depth=2**self.params.rob_entries_bits, init=[])
+        self.data = memory.Memory(shape=layouts.data_layout.size, depth=2**self.params.rob_entries_bits, init=[])
         self.get_indices = Method(o=layouts.get_indices, nonexclusive=True)
 
         self.perf_rob_wait_time = FIFOLatencyMeasurer(

coreblocks/peripherals/wishbone.py

@@ -1,5 +1,5 @@
 from amaranth import *
-from amaranth.lib.memory import Memory
+import amaranth.lib.memory as memory
 from amaranth.lib.wiring import PureInterface, Signature, In, Out, Component
 from functools import reduce
 from typing import Protocol, cast
@@ -527,7 +527,7 @@ def __init__(self, wb_params: WishboneParameters, **kwargs):
         if self.granularity not in (8, 16, 32, 64):
             raise RuntimeError("Granularity has to be one of: 8, 16, 32, 64")
 
-        self.mem = Memory(**kwargs)
+        self.mem = memory.Memory(**kwargs)
 
     def elaborate(self, platform):
         m = TModule()

test/peripherals/test_wishbone.py

@@ -386,7 +386,7 @@ def write_process():
                 yield Tick()
 
                 if req["we"]:
-                    assert (yield self.m.mem_slave.mem.data[req["addr"]]) == mem_state[req["addr"]]
+                    assert (yield Value.cast(self.m.mem_slave.mem.data[req["addr"]])) == mem_state[req["addr"]]
 
         with self.run_simulation(self.m, max_cycles=3000) as sim:
             sim.add_process(request_process)

test/scheduler/test_scheduler.py

@@ -270,7 +270,10 @@ def make_output_process(self, io: TestbenchIO, output_queues: Iterable[deque]):
         def check(got, expected):
             rl_dst = yield View(
                 self.gen_params.get(ROBLayouts).data_layout,
-                C((yield self.m.rob.data.data[got["rs_data"]["rob_id"]]), self.gen_params.get(ROBLayouts).data_layout.size),
+                C(
+                    (yield Value.cast(self.m.rob.data.data[got["rs_data"]["rob_id"]])),
+                    self.gen_params.get(ROBLayouts).data_layout.size,
+                ),
             ).rl_dst
             s1 = self.rf_state[expected["rp_s1"]]
             s2 = self.rf_state[expected["rp_s2"]]

transactron/lib/fifo.py

@@ -1,5 +1,5 @@
 from amaranth import *
-from amaranth.lib.memory import Memory
+import amaranth.lib.memory as memory
 from transactron import Method, def_method, Priority, TModule
 from transactron.utils._typing import ValueLike, MethodLayout, SrcLoc, MethodStruct
 from transactron.utils.amaranth_ext import mod_incr
@@ -49,7 +49,7 @@ def __init__(self, layout: MethodLayout, depth: int, *, src_loc: int | SrcLoc =
         self.clear = Method(src_loc=src_loc)
         self.head = Signal(from_method_layout(layout))
 
-        self.buff = Memory(shape=self.width, depth=self.depth, init=[])
+        self.buff = memory.Memory(shape=self.width, depth=self.depth, init=[])
 
         self.write_ready = Signal()
         self.read_ready = Signal()

transactron/lib/storage.py

@@ -1,6 +1,6 @@
 from amaranth import *
 from amaranth.utils import *
-from amaranth.lib.memory import Memory
+import amaranth.lib.memory as memory
 
 from transactron.utils.transactron_helpers import from_method_layout, make_layout
 from ..core import *
@@ -79,7 +79,7 @@ def __init__(
     def elaborate(self, platform) -> TModule:
         m = TModule()
 
-        m.submodules.mem = mem = Memory(shape=self.width, depth=self.elem_count, init=[])
+        m.submodules.mem = mem = memory.Memory(shape=self.width, depth=self.elem_count, init=[])
         write_port = mem.write_port()
         read_port = mem.read_port(transparent_for=[write_port] if self.transparent else [])
         read_output_valid = Signal()
@@ -272,7 +272,7 @@ def __init__(
     def elaborate(self, platform) -> TModule:
         m = TModule()
 
-        mem = Memory(shape=self.width, depth=self.elem_count, init=[])
+        mem = memory.Memory(shape=self.width, depth=self.elem_count, init=[])
         m.submodules.mem = mem
         write_port = mem.write_port()
         read_port = mem.read_port(domain="comb")