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FPU rounding module #2974

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FPU rounding module

FPU rounding module #2974

Triggered via pull request October 6, 2024 01:53
@DurchbruchswagenDurchbruchswagen
synchronize #728
Durchbruchswagen:fpu_rounding
Status Success
Total duration 13m 27s
Artifacts 1

main.yml

on: pull_request
Synthesize full core
30s
Synthesize full core
Build regression tests (riscv-tests)
46s
Build regression tests (riscv-tests)
Build regression tests (riscv-arch-test)
51s
Build regression tests (riscv-arch-test)
Run unit tests
6m 18s
Run unit tests
Check code formatting and typing
42s
Check code formatting and typing
Run regression tests (riscv-tests)
3m 19s
Run regression tests (riscv-tests)
Run regression tests (riscv-arch-test)
12m 17s
Run regression tests (riscv-arch-test)
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Artifacts

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Name Size
verilog-full-core
345 KB