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Implement full mtval #2969

Implement full mtval

Implement full mtval #2969

Triggered via pull request October 5, 2024 15:43
Status Success
Total duration 13m 18s
Artifacts 1

main.yml

on: pull_request
Synthesize full core
27s
Synthesize full core
Build regression tests (riscv-tests)
39s
Build regression tests (riscv-tests)
Build regression tests (riscv-arch-test)
41s
Build regression tests (riscv-arch-test)
Run unit tests
6m 53s
Run unit tests
Check code formatting and typing
46s
Check code formatting and typing
Run regression tests (riscv-tests)
3m 27s
Run regression tests (riscv-tests)
Run regression tests (riscv-arch-test)
12m 20s
Run regression tests (riscv-arch-test)
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Artifacts

Produced during runtime
Name Size
verilog-full-core
349 KB