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FPU rounding module #2965

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FPU rounding module

FPU rounding module #2965

Triggered via pull request October 1, 2024 17:12
@DurchbruchswagenDurchbruchswagen
synchronize #728
Durchbruchswagen:fpu_rounding
Status Success
Total duration 14m 19s
Artifacts 1

main.yml

on: pull_request
Synthesize full core
53s
Synthesize full core
Build regression tests (riscv-tests)
46s
Build regression tests (riscv-tests)
Build regression tests (riscv-arch-test)
46s
Build regression tests (riscv-arch-test)
Run unit tests
7m 38s
Run unit tests
Check code formatting and typing
40s
Check code formatting and typing
Run regression tests (riscv-tests)
3m 54s
Run regression tests (riscv-tests)
Run regression tests (riscv-arch-test)
13m 2s
Run regression tests (riscv-arch-test)
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Artifacts

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Name Size
verilog-full-core
455 KB