Skip to content
CI

FPU rounding module #2964

Sign in to view logs

FPU rounding module

FPU rounding module #2964

Triggered via pull request October 1, 2024 16:56
@DurchbruchswagenDurchbruchswagen
synchronize #728
Durchbruchswagen:fpu_rounding
Status Success
Total duration 14m 9s
Artifacts 1

main.yml

on: pull_request
Synthesize full core
55s
Synthesize full core
Build regression tests (riscv-tests)
37s
Build regression tests (riscv-tests)
Build regression tests (riscv-arch-test)
39s
Build regression tests (riscv-arch-test)
Run unit tests
7m 27s
Run unit tests
Check code formatting and typing
34s
Check code formatting and typing
Run regression tests (riscv-tests)
3m 48s
Run regression tests (riscv-tests)
Run regression tests (riscv-arch-test)
12m 54s
Run regression tests (riscv-arch-test)
Fit to window
Zoom out
Zoom in

Artifacts

Produced during runtime
Name Size
verilog-full-core
455 KB