Enable RoCC instructions after context switches #3
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Unfortunately, I can't recreate this in Spike right now. I'll keep this PR open in the short-term as a reminder that this might happen (and still needs investigating). |
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Hi, Thank you very much to identify this hidden bug. However, I think your update does not fix the issue, as my test still fails in the ROCC instructions with P-Thread. I did many tests, and pretty sure that there are some ROCC instructions are missed (at least missed the XS bits). I am using the BOOM version: ad64c5419151e5e886daee7084d8399713b46b4b |
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When using pthreads with cores having RoCC instructions, context switches clear the XS bit causing illegal instruction program failures. This fix forces the XS bit to be set whenever a context switch is done to avoid this issue.