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Update stfs-writer to the latest master #44
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Commits on May 22, 2022
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Commits on May 23, 2022
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[GPU] Decompress GBGR/BGRG into RGBB, not RGB1
While the alpha of the texture data is not used at all (replaced with blue using the view swizzle), still make the shader code state the intention more explicitly if the format is decompressed for use as signed. Unsigned 1.0 is 0xFF, while signed 1.0 is 0x7F.
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Commits on May 24, 2022
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[D3D12] Texture load code cleanup and resolution scaling fixes
The resolution scale is now taken into account when copying from the mip tail.
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Commits on May 27, 2022
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Commits on May 31, 2022
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Commits on Jun 1, 2022
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Commits on Jun 2, 2022
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Commits on Jun 6, 2022
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Commits on Jun 9, 2022
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Commits on Jun 11, 2022
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Commits on Jun 12, 2022
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[GPU] Fix missing xenia-ui dependency in gpu > gpu-shader-compiler (n…
…eeded for gmake2)
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Commits on Jun 19, 2022
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Commits on Jun 20, 2022
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[GPU] Make resolve EDRAM binding DS 0 and rename it
Ordering the descriptor sets by the change frequency on Vulkan, in increasing order (the opposite of D3D12 root signatures). The EDRAM binding never changes there (always one storage buffer), while the destination buffer binding may become changeable in the future (to split dispatches if exceeding `maxStorageBufferRange`, for example).
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[GPU] Separate range arguments for fixed16 RG and RGBA in GetResolveInfo
On Vulkan, when snorm16 in unsupported, these formats may be emulated as float16, which natively can represent a wide range of numbers including -32 to 32 with blending. However, R16G16_SNORM and R16G16B16A16_SNORM are two separate formats, which may have different support on the device.
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[Vulkan] Use UDiv/UMod by constant tile size + minor transfer cleanup
Drivers compile that to a multiplication and a shift anyway.
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[D3D12] Use udiv by constant tile size + minor transfer cleanup
Drivers compile that to a multiplication and a shift anyway.
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Commits on Jun 21, 2022
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Commits on Jun 22, 2022
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[D3D12] Truncate depth to float24 in EDRAM range ownership transfers …
…and resolves by default Doesn't ruin the "greater or equal" depth test in subsequent rendering passes if precision is lost, unlike rounding to the nearest
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[Vulkan] Truncate depth to float24 in EDRAM range ownership transfers…
… and resolves by default Doesn't ruin the "greater or equal" depth test in subsequent rendering passes if precision is lost, unlike rounding to the nearest
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[GPU] Safer and more correct depth bias conversion
Float24-as-float32 depth bias is now in the increments of 8, because conversion of the depth to float24 directly in the pixel shaders may destroy the bias qualitatively otherwise if it's too small.
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Commits on Jun 23, 2022
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Commits on Jun 25, 2022
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[Vulkan] Remove UB-based independent blend logic
On Vulkan, unlike Direct3D, not writing to a color target in the fragment shader produces an undefined result.
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Commits on Jun 26, 2022
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[GPU] Explicitly cast bit field values in std::min/max
According to the integral promotion rules https://eel.is/c++draft/conv.prom#5.sentence-1 bit fields can be promoted to `int` if it's wide enough to store their value, and then otherwise, to `unsigned int`. Hopefully fixes Clang building (the `width_div_8` case).
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[GPU] Apply BaseMap MipFilter via samplers as it may be overridden
Make it have no effect on the texture resource as a resource may be used with samplers with different overrides. Also make sure magnification vs. minification is not undefined with it on Direct3D 12.
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Commits on Jun 28, 2022
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[GPU] Align texture extents in loading to host buffer texel size acce…
…ssed by the shader
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[Vulkan] Align texture extents in loading to vector size accessed by …
…the shader Fixes loading of the 1x1 linear 8_8_8_8 texture containing just a single #FFFFFFFF texel in 4D5307E6, which is used for screen fade and the lobby map loading bar background
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Commits on Jun 30, 2022
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[GPU] Display swap output in the trace viewer
Resolve output is unreliable because resolving may be done to a subregion of a texture and even to 3D textures, and to any color format
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[Vulkan] Remove required feature checks
Fallbacks for those will be added more or less soon, the stable version won't hard-require anything beyond 1.0 and the portability subset
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[Drone] Windowed apps are not yet ready for Android building (kind Wi…
…ndowedApp unsupported)
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Revert "[GPU] Make Processor optional for GraphicsSystem setup"
The Processor is still required in many places, including the GPU command processor worker thread This reverts commit fd03d88.
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Commits on Jul 7, 2022
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[Vulkan] All guest draw uniform buffer bindings in a single descripto…
…r set Reduce the number of bound descriptor sets from 10 to 6, which is still above the minimum limit of 4, but closer
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Commits on Jul 9, 2022
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[Vulkan] Merge texture and sampler descriptors into a single descript…
…or set Put all descriptors used by translated shaders in up to 4 descriptor sets, which is the minimum required, and the most common on Android, `maxBoundDescriptorSets` device limit value
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Commits on Jul 14, 2022
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[Base] PosixMappedMemory: fd instead of stdio
Android ContentResolver, which is needed for content:// URIs, provides file descriptors rather than stdio files
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Commits on Jul 16, 2022
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[Android] Don't require the storage permission
GPU traces in the trace viewer are accessed via the Storage Access Framework, which doesn't require the storage permissions. Games will be accessed using the SAF too (directories containing games as document trees with persistable URI permissions). The storage permissions are also not required for accessing the application's external or internal storage directory that will contain the save files.
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Commits on Jul 21, 2022
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[GPU] Eliminate unused shader I/O, UCP culling, centroid on Vulkan
For more optimal usage of exports and the parameter cache on the host regardless of how effective the optimizations in the host GPU driver are. Also reserve space for Vulkan/Metal/D3D11-specific HostVertexShaderTypes to use one more bit for the host vertex shader type in the shader modification bits, so that won't have to be done in the future as that would require invalidating shader storages (which are invalidated by this commit) again.
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Use variable for Python version to make upgrading easier. xb.bat: Update copyright date. Add candidate paths. xb.ps1 Properly use found python executable. More consistency with .bat. Don't spew unnecessary errors, etc. EOF newline.
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[PPC] Fix memory assert formatting
This was still using printf-style format specifiers. Causing memory asserts to show up like this while testing. ``` !> 0000438C Memory 10001040 assert failed: !> 0000438C Expected: %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X !> 0000438C Actual: %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X !> 0000438C TEST FAILED ``` Updated them so they format correctly: ``` !> 00002CCC Memory 10001040 assert failed: !> 00002CCC Expected: FC FD FE FF 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F !> 00002CCC Actual: FC FD FE FF 00 00 00 00 00 00 00 00 00 00 00 00 !> 00002CCC TEST FAILED ```
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[x64] Add AVX512 optimization for
OPCODE_VECTOR_CONVERT_F2I
(unsigned)`vcvttps2udq` already saturates overflowing and unordered values to `0xFFFFFFFF`. Using mask registers, zeroes are written to negative values within the same instruction.
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[x64] Add AVX512 optimization for
OPCODE_VECTOR_ADD
(saturated)Uses a single `vpternlogd` to test for signed/unsigned overflow/underflow. Then utilizes AVX512 mask operations to create either `0x7FFFFFFF` or `0x80000000` arithmetically.
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[Premake] Update premake-cmake
- Handle compiler flags per-file. Removes ffmpeg warnings - Switch to JoelLinn fork since original author stopped maintaining and other forks don't seem to care about PRs
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[GPU] Vulkan fragment shader interlock RB and related fixes/cleanup
Also fixes addressing of MSAA samples 2 and 3 for 64bpp color render targets in the ROV RB implementation on Direct3D 12. Additionally, with FSI/ROV, alpha test and alpha to coverage are done only if the render target 0 was dynamically written to (according to the Direct3D 9 rules for writing to color render targets, though not sure if they actually apply to the alpha tests on Direct3D 9, but for safety). There is also some code cleanup for things spotted during the development of the feature.
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[DXBC] Fix interpolator copying from v# to r# in PS
The bit count was of `(1<<i)-1` itself (thus couldn't handle interpolators with a smaller index skipped), not of `bits&((1<<i)-1)`.
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[x64] Add AVX512 optimization for
OPCODE_VECTOR_SUB
(saturated)Passes the `vsubuws` and `vsubsws` unit-tests from xenia-project#1348
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[x64] Add
kX64EmitAVX512VBMI
feature-flag and detectionAllows access to byte-element 2-register permutations(32-byte look up tables) and for 64-bit multi-shifts. Particularly adding this to accelerate the assembly of our `PERMUTE` opcode.
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[x64] Add AVX512 optimizations for
PERMUTE_V128
Uses the single-instruction AVX512 `vperm*` instructions to accelerate the `INT8_TYPE` and `INT16_TYPE` permutation opcodes. The `INT8_TYPE` is accelerated using `AVX512VBMI` subset of AVX512. Available since Icelake(Intel) and Zen4(AMD).
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[D3D12] Replace unused shared memory view with a null view
Fixes the PIX validation warning about missing resource states on every guest draw. Also potentially prevents drivers from making assumptions about the shared memory buffer based on the bindings, though no such cases are currently known.
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[GPU] Fix tiled mip tail extent calculation
Previously, for mips, the dimensions of the texture weren't rounded to powers of two before calculating the mip tail extent, resulting in the mip tail for a 260 blocks tall texture, that contains mips ending at Y of up to 36, having the Y extent calculated as 32. With rounding to powers of two, it would have been 64. However, with the GetTiledAddressUpperBound functions, none of this is necessary at all (and neither is rounding the extents in TextureGuestLayout::Level to 32x32x4 blocks) - using the same code for calculating the XYZ extents of tiled textures as for linear textures now, which, for the mip tail, calculates the actual maximum coordinates of the mips stored in it - and rounding to tiles is done internally by GetTiledAddressUpperBound.
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[UI] Fix ClearInput not called in ImGuiDrawer after deferred dialog r…
…emoval Also cleanup the code involved in dialog registration, and update the explanation of why dialog removal is delayed until the end of drawing (the original was written back when window listener and UI drawer callback registration during the execution of the callbacks was deferred, but that was wrong as that might result in execution of callbacks belonging to now-deleted objects).
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[SPIR-V] Decorate whole gl_PerVertex with Invariant
Block members can be decorated with Invariant only since SPIR-V 1.5 Revision 2. In earlier versions, Invariant can be used only for variables. Mesa warns about this.
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[UI] Fix UB (moved mem) in file picker
- References to vector data become UB after vector size changes. - Add one extra level of indirection to pin the wide string memory location regardless of vector memory
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[CPU] Increase amount of possible labels used in FinalizationPass
Instead of using decimal notaation for labels let's use hexadecimal. That will increase amount of possible combination by a lot.
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Used to help with generating instruction-specific constants. Currently used for the ternary-logic constants(`vpternlog*`).
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[x64] Add AX512 optimization for
OPCODE_SELECT
(V128)Uses `vpternlogd` to collapse the bitwise select operation into one instruction. Though it needs a `vmovdqa` instruction since `vpternlogd` reads and writes to the first argument.
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Commits on Dec 31, 2022
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Commits on Feb 6, 2023
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[Build] Add parallel PPC test generation
Utilizes `multiprocessing` to allow for multiple power-pc assembly tests to be generated in parallel. Some results on my i9-11900k(8c/16t): Before: ``` Measure-Command {.\xb gentests} Days : 0 Hours : 0 Minutes : 0 Seconds : 11 Milliseconds : 200 Ticks : 112007585 TotalDays : 0.000129638408564815 TotalHours : 0.00311132180555556 TotalMinutes : 0.186679308333333 TotalSeconds : 11.2007585 TotalMilliseconds : 11200.7585 ``` After: ``` Measure-Command {.\xb gentests} Days : 0 Hours : 0 Minutes : 0 Seconds : 5 Milliseconds : 426 Ticks : 54265895 TotalDays : 6.28077488425926E-05 TotalHours : 0.00150738597222222 TotalMinutes : 0.0904431583333333 TotalSeconds : 5.4265895 TotalMilliseconds : 5426.5895 ``` This is an over **x2** speedup!
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Commits on Apr 9, 2023
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[DXBC]
discard
pixels fromkill
with ROV instead of returningKeep the current lane active as it may be needed for derivatives.
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Commits on Apr 13, 2023
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Commits on May 5, 2023
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[GPU/D3D12] Memexport from anywhere in control flow + 8/16bpp memexport
There's no limit on the number of memory exports in a shader on the real Xenos, and exports can be done anywhere, including in loops. Now, instead of deferring the exports to the end of the shader, and assuming that export allocs are executed only once, Xenia flushes exports when it reaches an alloc (allocs terminate memory exports on Xenos, as well as individual ALU instructions with `serialize`, but not handling this case for simplicity, it's only truly mandatory to flush memory exports before starting a new one), the end of the shader, or a pixel with outstanding exports is killed. To know which eM# registers need to be flushed to the memory, traversing the successors of each exec potentially writing any eM#, and specifying that certain eM# registers might have potentially been written before each reached control flow instruction, until a flush point or the end of the shader is reached. Also, some games export to sub-32bpp formats. These are now supported via atomic AND clearing the bits of the dword to replace followed by an atomic OR inserting the new byte/short.
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[GPU] Remove a dangerous comment about break after exece [ci skip]
There can be jumps across an exece, so the code beyond it may still be executed.
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I don't know of any title that utilizes this instruction, but I went ahead and implemented it for completeness. Verified the implementation with `instr__gen_vaddcuw` from xenia-project#1348. Can be grabbed with: ``` git checkout origin/gen_tests -- src\xenia\cpu\ppc\testing\*vaddcuw.s ```
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Other half of xenia-project#2125. I don't know of any title that utilizes this instruction, but I went ahead and implemented it for completeness. Verified the implementation with `instr__gen_vsubcuw` from xenia-project#1348. Can be grabbed with: ``` git checkout origin/gen_tests -- src\xenia\cpu\ppc\testing\*vsubcuw.s ```
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[x64] Add AVX512 optimizations for
OPCODE_VECTOR_COMPARE_UGT
(Integer)AVX512 has native unsigned integer comparisons instructions, removing the need to XOR the most-significant-bit with a constant in memory to use the signed comparison instructions. These instructions only write to a k-mask register though and need an additional call to `vpmovm2*` to turn the mask-register into a vector-mask register. As of Icelake: `vpcmpu*` is all L3/T1 `vpmovm2d` is L1/T0.33 `vpmovm2{b,w}` is L3/T0.33 As of Zen4: `vpcmpu*` is all L3/T0.50 `vpmovm2*` is all L1/T0.25
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[NET] NetDll___WSAFDIsSet: Fixed incorrect endianness of fd_count
Plus: limit it to 64 entries Thanks to Bo98 for pointing that out
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Commits on Jul 8, 2023
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