Modify pipeline of mkUdpIpStreamForRdma

fpga/XdmaUdpCmacPerfTest/Makefile

@@ -16,8 +16,8 @@ QSFP_IDX = 1
 ENABLE_CMAC_RSFEC = 1
 ENABLE_ARP_PROCESS = 0
 ENABLE_BYPASS_MODE = 1
-ENABLE_DEBUG_MODE = 1
-SUPPORT_RDMA ?= False
+ENABLE_DEBUG_MODE = 0
+SUPPORT_RDMA ?= True
 
 MACROFLAGS = -D IS_SUPPORT_RDMA=$(SUPPORT_RDMA)
 

fpga/XdmaUdpCmacPerfTest/tcl/synth_impl_opts.tcl

@@ -1,5 +1,5 @@
 
-#set synth_opts "-directive PerformanceOptimized -resource_sharing off -shreg_min_size 5 -no_lc -keep_equivalent_registers"
-#set place_opts "-directive ExtraNetDelay_high"
+set synth_opts "-directive PerformanceOptimized -resource_sharing off -shreg_min_size 5 -no_lc -keep_equivalent_registers"
+set place_opts "-directive ExtraNetDelay_high"
 #set route_opts "-directive NoTimingRelaxation"
 #set phys_opt_opts "-directive AggressiveExplore"

fpga/common/tcl/non_proj_build.tcl

@@ -132,7 +132,7 @@ proc runPostSynthReport {args} {
 
 
 proc runPlacement {args} {
-    global dir_output place_opts
+    global dir_output place_opts phys_opt_opts
 
     if {[dict get $args -open_checkpoint]} {
         open_checkpoint $dir_output/post_synth_design.dcp

src/UdpIpLayerForRdma.bsv

@@ -3,6 +3,7 @@ import FIFOF :: *;
 import Ports :: *;
 import EthUtils :: *;
 import UdpIpLayer :: *;
+import Connectable :: *;
 import EthernetTypes :: *;
 import StreamHandler :: *;
 
@@ -97,12 +98,13 @@ module mkUdpIpStreamForRdma#(
     DataStreamFifoOut dataStreamIn,
     UdpConfig udpConfig
 )(DataStreamFifoOut);
-
+    Integer udpIpStreamInterBufDepth = 16;
     FIFOF#(DataStream) dataStreamBuf <- mkFIFOF;
     FIFOF#(DataStream) dataStreamCrcBuf <- mkFIFOF;
     FIFOF#(UdpIpMetaData) udpIpMetaDataBuf <- mkFIFOF;
     FIFOF#(UdpIpMetaData) udpIpMetaDataCrcBuf <- mkFIFOF;
     FIFOF#(UdpLength) preComputeLengthBuf <- mkFIFOF;
+    FIFOF#(DataStream) udpIpStreamInterBuf <- mkSizedFIFOF(udpIpStreamInterBufDepth);
 
     rule forkUdpIpMetaDataIn;
         let udpIpMetaData = udpIpMetaDataIn.first;
@@ -128,6 +130,7 @@ module mkUdpIpStreamForRdma#(
         convertFifoToFifoOut(udpIpMetaDataBuf),
         genUdpIpHeaderForRoCE
     );
+    mkConnection(udpIpStream, convertFifoToFifoIn(udpIpStreamInterBuf));
 
     DataStreamFifoOut udpIpStreamForICrc <- mkUdpIpStreamForICrcGen(
         convertFifoToFifoOut(udpIpMetaDataCrcBuf),
@@ -143,7 +146,7 @@ module mkUdpIpStreamForRdma#(
     DataStreamFifoOut udpIpStreamWithICrc <- mkAppendDataStreamTail(
         HOLD,
         HOLD,
-        udpIpStream,
+        convertFifoToFifoOut(udpIpStreamInterBuf),
         crc32Stream,
         convertFifoToFifoOut(preComputeLengthBuf)
     );
@@ -272,9 +275,9 @@ module mkRemoveICrcFromDataStream#(
 endmodule
 
 typedef 4096 RDMA_PACKET_MAX_SIZE;
-typedef 3 RDMA_META_BUF_SIZE;
-typedef TDiv#(RDMA_PACKET_MAX_SIZE, DATA_BUS_BYTE_WIDTH) RDMA_PACKET_MAX_FRAME;
-typedef TAdd#(RDMA_PACKET_MAX_FRAME, 16) RDMA_PAYLOAD_BUF_SIZE;
+typedef 4 RDMA_META_BUF_SIZE;
+typedef TDiv#(RDMA_PACKET_MAX_SIZE, DATA_BUS_BYTE_WIDTH) RDMA_PACKET_MAX_BEAT;
+typedef TAdd#(RDMA_PACKET_MAX_BEAT, 16) RDMA_PAYLOAD_BUF_SIZE;
 
 typedef enum {
     ICRC_IDLE,

test/bluesim/TestUdpIpEthBypassRxTx.bsv

@@ -13,7 +13,6 @@ import UdpIpEthCmacRxTx :: *;
 
 import SemiFifo :: *;
 
-
 typedef 32 CYCLE_COUNT_WIDTH;
 typedef 16 CASE_COUNT_WIDTH;
 typedef 100000 MAX_CYCLE_NUM;
@@ -25,9 +24,9 @@ typedef 32'h00000000 DUT_NET_MASK;
 typedef 32'h00000000 DUT_GATE_WAY;
 
 typedef 7 BEAT_COUNT_WIDTH;
-typedef 4 MAX_AXI_STREAM_DELAY;
+typedef 0 MAX_AXI_STREAM_DELAY;
 
-typedef 256 REF_BUF_DEPTH;
+typedef 1024 REF_BUF_DEPTH;
 
 (* synthesize *)
 module mkTestUdpIpEthBypassRxTx();
@@ -36,9 +35,15 @@ module mkTestUdpIpEthBypassRxTx();
 
     // Common Signals
     Reg#(Bool) isInit <- mkReg(False);
-    Reg#(Bit#(CYCLE_COUNT_WIDTH)) cycleCount <- mkReg(0);
+    Reg#(Bit#(CYCLE_COUNT_WIDTH)) cycleCounter <- mkReg(0);
     Reg#(Bit#(CASE_COUNT_WIDTH)) inputCaseCounter <- mkReg(0);
     Reg#(Bit#(CASE_COUNT_WIDTH)) outputCaseCounter <- mkReg(0);
+    Reg#(Bit#(CYCLE_COUNT_WIDTH)) txChannelStartCycleIdx <- mkRegU;
+    Reg#(Bit#(CYCLE_COUNT_WIDTH)) rxChannelStartCycleIdx <- mkRegU;
+    Reg#(Bit#(CYCLE_COUNT_WIDTH)) txChannelEndCycleIdx <- mkRegU;
+    Reg#(Bit#(CYCLE_COUNT_WIDTH)) rxChannelEndCycleIdx <- mkRegU;
+    Reg#(Bit#(CYCLE_COUNT_WIDTH)) rxBlockCycle <- mkReg(0);
+    Reg#(Bit#(CYCLE_COUNT_WIDTH)) txBlockCycle <- mkReg(0);
 
     // Random Signals
     Randomize#(Data) randData <- mkGenericRandomizer;
@@ -93,18 +98,20 @@ module mkTestUdpIpEthBypassRxTx();
 
     // Count Cycle Number
     rule doCycleCount if (isInit);
-        cycleCount <= cycleCount + 1;
-        $display("\nCycle %d ----------------------------------------", cycleCount);
+        cycleCounter <= cycleCounter + 1;
+        $display("\nCycle %d ----------------------------------------", cycleCounter);
         immAssert(
-            cycleCount < fromInteger(maxCycleNum),
+            cycleCounter < fromInteger(maxCycleNum),
             "Testbench timeout assertion @ mkTestPfcUdpIpArpEthRxTx",
             $format("Cycle number overflow %d", maxCycleNum)
         );
     endrule
 
     rule sendMetaData if (isInit && !metaDataSentFlag && inputCaseCounter < fromInteger(testCaseNum));  
-        let beatNum <- randBeatNum.next;
-        let bypassSelect <- randBypassSelect.next;
+        // Bit#(BEAT_COUNT_WIDTH) beatNum <- randBeatNum.next;
+        Bit#(BEAT_COUNT_WIDTH) beatNum = 32;
+        //Bool bypassSelect <- randBypassSelect.next;
+        Bool bypassSelect = False;
         if (beatNum == 0) beatNum = 1;
         beatNumReg <= beatNum;
         bypassSelectReg <= bypassSelect;
@@ -148,6 +155,7 @@ module mkTestUdpIpEthBypassRxTx();
             refUdpIpMetaDataBuf.enq(udpIpMetaData);
             $display("Testbench: Testcase %d sends UdpIpMetaData and MacMetaData to packet generator", inputCaseCounter);
         end
+        if (inputCaseCounter == 0) txChannelStartCycleIdx <= cycleCounter;
     endrule
 
     rule sendDataStream if (metaDataSentFlag);
@@ -171,6 +179,9 @@ module mkTestUdpIpEthBypassRxTx();
         if (dataStream.isLast) begin
             metaDataSentFlag <= False;
             inputCaseCounter <= inputCaseCounter + 1;
+            if (inputCaseCounter == fromInteger(testCaseNum) - 1) begin
+                txChannelEndCycleIdx <= cycleCounter;
+            end
         end
 
         $display("Testbench: Sends %d DataStream of %d testcase", inputBeatCounter, inputCaseCounter);
@@ -231,10 +242,19 @@ module mkTestUdpIpEthBypassRxTx();
         else begin
             outputBeatCounter <= outputBeatCounter + 1;
         end
+        if (outputBeatCounter == 0 && outputCaseCounter == 0) begin
+            rxChannelStartCycleIdx <= cycleCounter;
+        end
+        if (dutDataStream.isLast && outputCaseCounter == (fromInteger(testCaseNum) - 1)) begin
+            rxChannelEndCycleIdx <= cycleCounter;
+        end
     endrule
 
     rule finishTest if (outputCaseCounter == fromInteger(testCaseNum));
         $display("Testbench: mkUdpIpEthBypassRxTx pass all %5d testcases", testCaseNum);
+        $display("Duration of send input data: %d", txChannelEndCycleIdx - txChannelStartCycleIdx + 1);
+        $display("Duration of recv output data: %d", rxChannelEndCycleIdx - rxChannelStartCycleIdx + 1);
+        $display("Cycles of Rx channel Blocked: %d", rxBlockCycle);
         $finish;
     endrule
 endmodule

test/bluesim/TestUtils.bsv

@@ -8,30 +8,37 @@ import Ports :: *;
 import EthUtils :: *;
 import SemiFifo :: *;
 
+typedef 32 DELAY_COUNT_WIDTH;
 typedef Server#(
     dType, dType
 ) RandomDelay#(type dType, numeric type maxDelay);
 
-module mkRandomDelay(RandomDelay#(dType, delay)) 
+module mkRandomDelay(RandomDelay#(dType, maxDelay)) 
     provisos(Bits#(dType, sz));
-
+    Bit#(DELAY_COUNT_WIDTH) maxRandDelay = fromInteger(valueOf(maxDelay));
+
     FIFOF#(dType) buffer <- mkFIFOF;
     Reg#(Bool) hasInit <- mkReg(False);
-    Reg#(Bit#(TLog#(delay))) delayCounter <- mkReg(0);
-    Reg#(Bit#(TLog#(delay))) delayCountMax <- mkReg(0);
-    let passData = delayCounter == delayCountMax;
+    Reg#(Bit#(DELAY_COUNT_WIDTH)) delayCounter <- mkReg(0);
+    Reg#(Bit#(DELAY_COUNT_WIDTH)) randDelayReg <- mkReg(0);
+    let passData = delayCounter == randDelayReg;
 
-    Randomize#(Bit#(TLog#(delay))) delayRand <- mkGenericRandomizer;
+    Randomize#(Bit#(DELAY_COUNT_WIDTH)) delayRandomizer <- mkGenericRandomizer;
     rule doInit if (!hasInit);
-        delayRand.cntrl.init;
+        delayRandomizer.cntrl.init;
         hasInit <= True;
     endrule
 
     rule doCount;
-        if (delayCounter == delayCountMax) begin
+        if (delayCounter == randDelayReg) begin
             delayCounter <= 0;
-            Bit#(TLog#(delay)) randDelay <- delayRand.next;
-            delayCountMax <= randDelay;
+            let delay <- delayRandomizer.next;
+            if (valueOf(maxDelay) == 0) begin
+                randDelayReg <= 0;
+            end
+            else begin
+                randDelayReg <= delay > maxRandDelay ? maxRandDelay : delay;
+            end
         end
         else begin
             delayCounter <= delayCounter + 1;
@@ -46,7 +53,6 @@ module mkRandomDelay(RandomDelay#(dType, delay))
             return data;
         endmethod
     endinterface
-
 endmodule