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Merge pull request #540 from antmicro/kbieg/remove-uhdm-report
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Remove UHDM coverage report functionality
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Mariusz Glebocki authored Aug 29, 2023
2 parents 17519a6 + 5eb6ccc commit 5661b7d
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Showing 14 changed files with 2 additions and 277 deletions.
1 change: 0 additions & 1 deletion systemverilog-plugin/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,6 @@ SOURCES = UhdmAst.cc \
uhdmastfrontend.cc \
uhdmcommonfrontend.cc \
uhdmsurelogastfrontend.cc \
uhdmastreport.cc \
third_party/yosys/const2ast.cc \
third_party/yosys/simplify.cc

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25 changes: 0 additions & 25 deletions systemverilog-plugin/UhdmAst.cc
Original file line number Diff line number Diff line change
Expand Up @@ -1963,7 +1963,6 @@ void UhdmAst::make_cell(vpiHandle obj_h, AST::AstNode *cell_node, AST::AstNode *
}
});
cell_node->children.push_back(arg_node);
shared.report.mark_handled(port_h);
vpi_release_handle(port_h);
}
vpi_release_handle(port_itr);
Expand Down Expand Up @@ -2434,33 +2433,28 @@ void UhdmAst::process_typespec_member()
case vpiLogicTypespec: {
current_node->is_logic = true;
visit_one_to_many({vpiRange}, typespec_h, [&](AST::AstNode *node) { packed_ranges.push_back(node); });
shared.report.mark_handled(typespec_h);
break;
}
case vpiByteTypespec: {
current_node->is_signed = vpi_get(vpiSigned, typespec_h);
packed_ranges.push_back(make_range(7, 0));
shared.report.mark_handled(typespec_h);
break;
}
case vpiShortIntTypespec: {
current_node->is_signed = vpi_get(vpiSigned, typespec_h);
packed_ranges.push_back(make_range(15, 0));
shared.report.mark_handled(typespec_h);
break;
}
case vpiIntTypespec:
case vpiIntegerTypespec: {
current_node->is_signed = vpi_get(vpiSigned, typespec_h);
packed_ranges.push_back(make_range(31, 0));
shared.report.mark_handled(typespec_h);
break;
}
case vpiTimeTypespec:
case vpiLongIntTypespec: {
current_node->is_signed = vpi_get(vpiSigned, typespec_h);
packed_ranges.push_back(make_range(63, 0));
shared.report.mark_handled(typespec_h);
break;
}
case vpiStructTypespec:
Expand Down Expand Up @@ -3122,7 +3116,6 @@ void UhdmAst::process_array_net(const UHDM::BaseClass *object)
} else {
visit_one_to_many({vpiRange}, net_h, [&](AST::AstNode *node) { packed_ranges.push_back(node); });
}
shared.report.mark_handled(net_h);
} else if (net_type == vpiStructNet) {
visit_one_to_one({vpiTypespec}, net_h, [&](AST::AstNode *node) {
if (node->str.empty()) {
Expand Down Expand Up @@ -3865,7 +3858,6 @@ void UhdmAst::process_list_op()
log_error("Unhandled list op, couldn't find parent node.");
}
// Do not create a node
shared.report.mark_handled(obj_h);
}

void UhdmAst::process_cast_op()
Expand All @@ -3876,7 +3868,6 @@ void UhdmAst::process_cast_op()
delete node;
});
vpiHandle typespec_h = vpi_handle(vpiTypespec, obj_h);
shared.report.mark_handled(typespec_h);
vpi_release_handle(typespec_h);
}

Expand Down Expand Up @@ -4663,8 +4654,6 @@ void UhdmAst::process_port()
// Skip '\' in cellName
typeNode->str = ifaceName + '.' + cellName.substr(1, cellName.length());
current_node->children.push_back(typeNode);
shared.report.mark_handled(actual_h);
shared.report.mark_handled(iface_h);
vpi_release_handle(iface_h);
}
break;
Expand All @@ -4677,15 +4666,13 @@ void UhdmAst::process_port()
}
current_node->type = AST::AST_INTERFACEPORT;
current_node->children.push_back(typeNode);
shared.report.mark_handled(actual_h);
break;
}
case vpiLogicVar:
case vpiLogicNet: {
current_node->is_logic = true;
current_node->is_signed = vpi_get(vpiSigned, actual_h);
visit_one_to_many({vpiRange}, actual_h, [&](AST::AstNode *node) { packed_ranges.push_back(node); });
shared.report.mark_handled(actual_h);
break;
}
case vpiPackedArrayVar:
Expand All @@ -4699,15 +4686,12 @@ void UhdmAst::process_port()
delete node;
});
visit_one_to_many({vpiRange}, actual_h, [&](AST::AstNode *node) { packed_ranges.push_back(node); });
shared.report.mark_handled(actual_h);
break;
case vpiPackedArrayNet:
visit_one_to_many({vpiRange}, actual_h, [&](AST::AstNode *node) { packed_ranges.push_back(node); });
shared.report.mark_handled(actual_h);
break;
case vpiArrayVar:
visit_one_to_many({vpiRange}, actual_h, [&](AST::AstNode *node) { unpacked_ranges.push_back(node); });
shared.report.mark_handled(actual_h);
break;
case vpiEnumNet:
case vpiStructNet:
Expand All @@ -4730,7 +4714,6 @@ void UhdmAst::process_port()
break;
}
}
shared.report.mark_handled(lowConn_h);
vpi_release_handle(actual_h);
vpi_release_handle(lowConn_h);
}
Expand Down Expand Up @@ -4806,18 +4789,15 @@ void UhdmAst::process_parameter()
case vpiLogicTypespec: {
current_node->is_logic = true;
visit_one_to_many({vpiRange}, typespec_h, [&](AST::AstNode *node) { packed_ranges.push_back(node); });
shared.report.mark_handled(typespec_h);
break;
}
case vpiByteTypespec: {
packed_ranges.push_back(make_range(7, 0));
shared.report.mark_handled(typespec_h);
break;
}
case vpiEnumTypespec:
case vpiRealTypespec:
case vpiStringTypespec: {
shared.report.mark_handled(typespec_h);
break;
}
case vpiIntTypespec:
Expand All @@ -4826,18 +4806,15 @@ void UhdmAst::process_parameter()
if (packed_ranges.empty()) {
packed_ranges.push_back(make_range(31, 0));
}
shared.report.mark_handled(typespec_h);
break;
}
case vpiShortIntTypespec: {
packed_ranges.push_back(make_range(15, 0));
shared.report.mark_handled(typespec_h);
break;
}
case vpiTimeTypespec:
case vpiLongIntTypespec: {
packed_ranges.push_back(make_range(63, 0));
shared.report.mark_handled(typespec_h);
break;
}
case vpiStructTypespec: {
Expand All @@ -4859,7 +4836,6 @@ void UhdmAst::process_parameter()
}
case vpiPackedArrayTypespec:
case vpiArrayTypespec: {
shared.report.mark_handled(typespec_h);
visit_one_to_one({vpiElemTypespec}, typespec_h, [&](AST::AstNode *node) {
if (!node->str.empty()) {
auto wiretype_node = make_ast_node(AST::AST_WIRETYPE);
Expand Down Expand Up @@ -5350,7 +5326,6 @@ AST::AstNode *UhdmAst::process_object(vpiHandle obj_handle)
// Check if we initialized the node in switch-case
if (current_node) {
if (current_node->type != AST::AST_NONE) {
shared.report.mark_handled(object);
return current_node;
}
}
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2 changes: 0 additions & 2 deletions systemverilog-plugin/tests/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,6 @@ TESTS = counter \
break_continue \
separate-compilation \
debug-flag \
report-flag \
defines \
defaults \
formal \
Expand All @@ -30,7 +29,6 @@ counter_verify = true
break_continue_verify = $(call diff_test,break_continue,out)
separate-compilation_verify = true
debug-flag_verify = true
report-flag_verify = true
defaults_verify = true
defines_verify = true
formal_verify = true
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21 changes: 0 additions & 21 deletions systemverilog-plugin/tests/report-flag/report-flag-buf.sv

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19 changes: 0 additions & 19 deletions systemverilog-plugin/tests/report-flag/report-flag-pkg.sv

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14 changes: 0 additions & 14 deletions systemverilog-plugin/tests/report-flag/report-flag.tcl

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31 changes: 0 additions & 31 deletions systemverilog-plugin/tests/report-flag/report-flag.v

This file was deleted.

13 changes: 0 additions & 13 deletions systemverilog-plugin/uhdmastfrontend.cc
Original file line number Diff line number Diff line change
Expand Up @@ -47,21 +47,8 @@ struct UhdmAstFrontend : public UhdmCommonFrontend {
make_new_object_with_optional_extra_true_arg<UHDM::SynthSubset>(&serializer, this->shared.nonSynthesizableObjects, false);
synthSubset->listenDesigns(restoredDesigns);
delete synthSubset;
if (this->shared.debug_flag || !this->report_directory.empty()) {
for (auto design : restoredDesigns) {
std::ofstream null_stream;
#if UHDM_VERSION > 1057
UHDM::visit_object(design, this->shared.debug_flag ? std::cout : null_stream);
#else
UHDM::visit_object(design, 1, "", &this->shared.report.unhandled, this->shared.debug_flag ? std::cout : null_stream);
#endif
}
}
UhdmAst uhdm_ast(this->shared);
AST::AstNode *current_ast = uhdm_ast.visit_designs(restoredDesigns);
if (!this->report_directory.empty()) {
this->shared.report.write(this->report_directory);
}
for (auto design : restoredDesigns)
vpi_release_handle(design);

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90 changes: 0 additions & 90 deletions systemverilog-plugin/uhdmastreport.cc

This file was deleted.

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