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mglb/BumpSurelog; plugins: kr/adapt_surelog #4489

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mglb/BumpSurelog; plugins: kr/adapt_surelog

mglb/BumpSurelog; plugins: kr/adapt_surelog #4489

Manually triggered July 24, 2023 13:40
@mglbmglb
⁠ ea2e8ff
mglb/BumpSurelog
Status Failure
Total duration 47m 45s
Artifacts 18

main.yml

on: workflow_dispatch
Matrix: build-binaries
Build sv2v
1m 26s
Build sv2v
Emit Workflow Info
1m 21s
Emit Workflow Info
Style check
1m 9s
Style check
Parsing Tests  /  SystemVerilog Plugin
33m 30s
Parsing Tests / SystemVerilog Plugin
Matrix: Large Designs Tests / opentitan_parse_report
Large Designs Tests  /  Ibex (Vivado synthesis)
6m 29s
Large Designs Tests / Ibex (Vivado synthesis)
Large Designs Tests  /  Ibex (Symbiflow synthesis)
11m 0s
Large Designs Tests / Ibex (Symbiflow synthesis)
Large Designs Tests  /  Opentitan 9d82960888 (synthesis)
0s
Large Designs Tests / Opentitan 9d82960888 (synthesis)
Large Designs Tests  /  Opentitan (synthesis)
3m 56s
Large Designs Tests / Opentitan (synthesis)
Large Designs Tests  /  Swerv (synthesis)
5m 44s
Large Designs Tests / Swerv (synthesis)
Large Designs Tests  /  Black Parrot (synthesis)
26m 22s
Large Designs Tests / Black Parrot (synthesis)
Parsing Tests  /  Surelog
21m 40s
Parsing Tests / Surelog
Diff generated BSG Micro Designs tests  /  Parse and diff BSG Micro Designs
9m 35s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Matrix: Formal Verification Tests / tests-formal-verification
Parsing Tests  /  Generate AST diff
3m 59s
Parsing Tests / Generate AST diff
Parsing Tests  /  Summary Generation
1m 20s
Parsing Tests / Summary Generation
Formal Verification Tests  /  Passlist Check
1m 15s
Formal Verification Tests / Passlist Check
Release Package
0s
Release Package
Release Package Installation Test
0s
Release Package Installation Test
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Annotations

5 errors and 3 warnings
Large Designs Tests / Opentitan (synthesis)
Process completed with exit code 2.
Large Designs Tests / Opentitan parsing (quick)
Process completed with exit code 2.
Large Designs Tests / Opentitan parsing (full/top-down)
Process completed with exit code 2.
Formal Verification Tests / yosys
Process completed with exit code 1.
Parsing Tests / Surelog
An error occurred while attempting to read the response stream
Large Designs Tests / Opentitan (synthesis)
No files were found with the provided path: **/plot_*.svg. No artifacts will be uploaded.
Large Designs Tests / Swerv (synthesis)
No files were found with the provided path: UHDM-integration-tests/build/chipsalliance.org_cores_SweRV_EH1_1.8/synth-vivado/chipsalliance.org_cores_SweRV_EH1_1.8.edif. No artifacts will be uploaded.
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.

Artifacts

Produced during runtime
Name Size
binaries Expired
251 MB
binaries-asan Expired
1.29 GB
bp_e_bp_unicore_cfg.edif Expired
47.3 MB
bsg-logs Expired
94.9 MB
bsg-outputs Expired
11.6 MB
formal-verification-logs Expired
672 MB
formal-verification-tests-list Expired
59 KB
lowrisc_ibex_top_artya7_surelog_0.1.bit Expired
2.09 MB
opentitan-logs-full Expired
260 MB
opentitan-logs-quick Expired
113 MB
parsing_read-systemverilog_logs Expired
29.1 MB
parsing_read-systemverilog_yosys-sv Expired
380 KB
parsing_read-uhdm_logs Expired
68.2 KB
parsing_read-uhdm_yosys-sv Expired
376 KB
parsing_test-results Expired
15.4 KB
plots Expired
12.2 MB
sv2v Expired
8.3 MB
top_artya7.bit Expired
2.09 MB